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2011-02-04target-arm: Fix decoding of Thumb preload and hint spacePeter Maydell1-22/+48
Refine the decoding of the Thumb preload and hint space, so we UNDEF on the patterns that are supposed to UNDEF rather than NOP. We also move the tests for this space earlier, so we don't emit harmless but unnecessary address generation code for preload hints (which by their nature are likely to be in hot code paths). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04target-arm: Fix decoding of preload and memory hint spacePeter Maydell1-3/+25
Correct the decoding of the ARM preload and memory hint space, by adding decoding of PLI, PLDW and the v7MP unallocated hint space. This commit also corrects a slightly overexuberant decoding of PLD(register) which was not checking that bit 4 was one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04target-arm: Clean up handling of MPIDRPeter Maydell1-5/+21
The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architecture as the MPIDR. Clean up its implementation to remove A9 specific handling. This commit includes fixing an error in the value returned for the MPIDR on A9, where we were erroneously claiming a cluster ID of 9. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04target-arm: Add CPU feature flag for v7MPPeter Maydell2-1/+8
Add a CPU feature flag for v7MP (the multiprocessing extensions); some instructions exist only for v7MP and not for the base v7 architecture. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04Set the right overflow bit for neon 32 and 64 bit saturating add/sub.Christophe Lyon4-63/+105
Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04target-arm: Fix Neon vsra instructions.Christophe Lyon1-2/+2
This patch fixes the errors reported by my tests in VSRA. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-29target-arm: Fix Neon VQ(R)DMULH.S16 instructionsJuha Riihimäki1-1/+2
Correct an error in the implementation of the 16 bit forms of VQ(R)DMULH, bringing them into line with the 32 bit implementation. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-26target-arm: Fix loading of scalar value for Neon multiply-by-scalarPeter Maydell1-6/+6
Fix the register and part of register we get the scalar from in the various "multiply vector by scalar" ops (VMUL by scalar and friends). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-26target-arm: Fix garbage collection of temporaries in Neon emulation.Christophe Lyon1-5/+13
Fix garbage collection of temporaries in Neon emulation. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-26Support saturation with shift=0.Christophe Lyon1-16/+12
This patch fixes corner-case saturations, when the target range is zero. It merely removes the guard against (sh == 0), and makes: __ssat(0x87654321, 1) return 0xffffffff and set the saturation flag __usat(0x87654321, 0) return 0 and set the saturation flag Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-18target-arm: Log instruction start in TCG codePeter Maydell1-0/+4
Add support for logging the start of instructions in TCG code debug dumps for ARM targets. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-14target-arm: Restore IT bits when resuming after an exceptionPeter Maydell1-0/+36
We were not correctly restoring the IT bits when resuming execution after taking an unexpected exception in the middle of an IT block. Fix this by tracking them along with PC changes and restoring in gen_pc_load(). This fixes bug https://bugs.launchpad.net/qemu/+bug/581335 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Refactor translation of exception generating instructionsPeter Maydell1-28/+15
Create a new function which does the common sequence of gen_set_condexec, gen_set_pc_im, gen_exception, set is_jmp to DISAS_JUMP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Remove redundant setting of IT bits before Thumb SWIPeter Maydell1-1/+0
Remove a redundant call to gen_set_condexec() in the translation of Thumb mode SWI. (SWI and WFI generate "exceptions" which happen after the execution of the instruction, ie when PC and IT bits have updated. So the condexec bits at this point are not correct. However, the code that handles finishing the translation of the TB will write the correct value of the condexec bits later, so the only effect was that a conditional Thumb SWI would generate slightly worse code than necessary.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with user-state from TB flags, not CPUStatePeter Maydell1-5/+1
When translating, get the user/priv state from the TB flags, not the CPUState. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Set privileged bit in TB flags correctly for M profilePeter Maydell1-1/+7
M profile ARM cores don't have a CPSR mode field. Set the bit in the TB flags that indicates non-user mode correctly for these cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with condexec bits from TB flags, not CPUStatePeter Maydell1-3/+3
When translating, the condexec bits for the TB are in the TB flags; the CPUState condexec bits may be different. This patch fixes https://bugs.launchpad.net/bugs/604872 where we might segfault if we took an exception in the middle of a TB with an IT block, because when we came to retranslate in cpu_restore_state() the CPUState condexec bits would have advanced compared to the start of the TB and we would generate different (wrong) code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with Thumb state from TB flags, not CPUStatePeter Maydell1-3/+3
The Thumb/ARM state for the TB being translated should come from the TB flags, not the CPUState. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with VFP len/stride from TB flags, not CPUStatePeter Maydell1-3/+7
When translating, the VFP vector length and stride for this TB are encoded in the TB flags; the CPUState copies may be different and must not be used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with VFP-enabled from TB flags, not CPUStatePeter Maydell1-9/+5
When translating code, whether the VFP unit is enabled for this TB is stored in a bit in the TB flags. Use this rather than incorrectly reading the FPEXC from the CPUState passed to translation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Add symbolic constants for bitfields in TB flagsPeter Maydell1-6/+39
Add symbolic constants for the bitfields we use in the TB flags. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Don't generate code specific to current CPU mode for SRSPeter Maydell2-33/+25
When translating the SRS instruction, handle the "store registers to stack of current mode" case in the helper function rather than inline. This means the generated code does not make assumptions about the current CPU mode which might not be valid when the TB is executed later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Use the standard FPSCR value for VRSQRTSPeter Maydell1-1/+1
VSQRTS always uses the standard FPSCR value as it is a Neon instruction. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Add support for 'Standard FPSCR Value' as used by NeonPeter Maydell2-0/+18
Add support to the ARM helper routines for a second fp_status value which should be used for operations which the ARM ARM indicates use "ARM standard floating-point arithmetic" rather than being controlled by the rounding/flush/NaN settings in the FPSCR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Fix implementation of VRSQRTSPeter Maydell1-1/+9
The implementation of the ARM VRSQRTS instruction (which calculates (3 - op1 * op2) / 2) was missing the division operation. It also did not handle the special cases of (0,inf) and (inf,0). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-12ARM: Fix decoding of VQSHL/VQSHLU immediate formsPeter Maydell1-15/+36
Fix errors in the decoding of ARM VQSHL/VQSHLU immediate forms, including using the new VQSHLU helper functions where appropriate. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-12ARM: add neon helpers for VQSHLUJuha Riihimäki2-0/+51
Add neon helper functions to implement VQSHLU, which is a signed-to-unsigned version of VQSHL available only as an immediate form. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-06target-arm: wire up the softfloat flush_input_to_zero flagPeter Maydell1-1/+7
Wire up the new softfloat support for flushing input denormals to zero on ARM. The FPSCR FZ bit enables flush-to-zero for both inputs and outputs, but the reporting of when inputs are flushed to zero is via a separate IDC bit rather than the UFC (underflow) bit used when output denormals are flushed to zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-06target-arm: Set softfloat cumulative exc flags from correct FPSCR bitsPeter Maydell1-1/+1
When handling a write to the ARM FPSCR, set the softfloat cumulative exception flags from the cumulative flags in the FPSCR, not the exception-enable bits. Also don't apply a mask: vfp_exceptbits_to_host will only look at the correct bits anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-06target-arm: fix SMMLA/SMMLS instructionsAurelien Jarno1-45/+51
SMMLA and SMMLS are broken on both in normal and thumb mode, that is both (different) implementations are wrong. They try to avoid a 64-bit add for the rounding, which is not trivial if you want to support both SMMLA and SMMLS with the same code. The code below uses the same implementation for both modes, using the code from the ARM manual. It also fixes the thumb decoding that was a mix between normal and thumb mode. This fixes the issues reported in https://bugs.launchpad.net/qemu/+bug/629298 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-31target-arm: fix UMAAL instructionAurelien Jarno1-10/+22
UMAAL should use unsigned multiply instead of signed. This patch fixes this issue by handling UMAAL separately from UMULL/UMLAL/SMULL/SMLAL as these instructions are different enough. It also explicitly list instructions in case and catch nonexistent instruction as illegal. Also fixes a few style issues. This fixes the issues reported in https://bugs.launchpad.net/qemu/+bug/696015 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: correct cp15 c1_sys reset value for arm1136 and cortex-a9Juha Riihimäki1-0/+2
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: correct cp15 c1_sys reset value for cortex-a8Mattias Holm1-0/+1
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: fix vmsav6 access controlJuha Riihimäki1-15/+19
Override access control checks (including execute) for mmu translation table descriptors assigned to manager domains. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: Correct result in saturating cases for VQSHL of s8/16/32Peter Maydell1-3/+12
Where VQSHL of a signed 8/16/32 bit value saturated, the result value was not being calculated correctly (it should be either the minimum or maximum value for the size of the signed type). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: remove pointless else clause in VQSHL of u64Juha Riihimäki1-2/+0
Remove a pointless else clause in the neon_qshl_u64 helper. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: Fix VQSHL of signed 64 bit values by shift counts >= 64Peter Maydell1-1/+1
VQSHL of a signed 64 bit non-zero value by a shift count >= 64 should saturate; return the correct value in this case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: Fix VQSHL of signed 64 bit valuesJuha Riihimäki1-1/+1
Add a missing '-' which meant that we were misinterpreting the shift argument for VQSHL of 64 bit signed values and treating almost every shift value as if it were an extremely large right shift. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: Fix arguments passed to VQSHL helpersJuha Riihimäki1-2/+2
Correct the arguments passed when generating neon qshl_{u,s}64() helpers so that we use the correct registers. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: fix bug in translation of REVSHAurelien Jarno1-7/+3
The translation of REVSH shifted the low byte 8 steps left before performing an 8-bit sign extend, causing this part of the expression to alwas be 0. Reported-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-07ARM: Implement VCVT to 16 bit integer using new softfloat routinesPeter Maydell1-1/+1
Use the softfloat conversion routines for conversion to 16 bit integers, because just casting to a 16 bit type truncates the value rather than saturating it at 16-bit MAXINT/MININT. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Ignore top 16 bits when doing VCVT from 16 bit fixed pointPeter Maydell1-1/+1
VCVT of 16 bit fixed point to float should ignore the top 16 bits of the source register. Cast to int16_t and friends rather than int16 -- the former is guaranteed exactly 16 bits wide where the latter is merely at least 16 bits wide (and so is usually 32 bits). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Return correct result for single<->double conversion of NaNPeter Maydell1-2/+10
The ARM ARM defines that if the input to a single<->double conversion is a NaN then the output is always forced to be a quiet NaN by setting the most significant bit of the fraction part. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Return correct result for float-to-integer conversion of NaNPeter Maydell1-0/+27
The ARM architecture mandates that converting a NaN value to integer gives zero (if Invalid Operation FP exceptions are not being trapped). This isn't the behaviour of the SoftFloat library, so NaNs must be special-cased. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Fix sense of to_integer bit in Neon VCVT float/int conversionPeter Maydell1-4/+4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Fix decoding of Neon forms of VCVT between float and fixed pointPeter Maydell1-2/+6
Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Fix decoding of VFP forms of VCVT between float and int/fixedPeter Maydell1-7/+12
Correct the decoding of source and destination registers for the VFP forms of the VCVT instructions which convert between floating point and integer or fixed-point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: fix ldrexd/strexdPeter Maydell1-3/+5
Correct ldrexd and strexd code to always read and write the high word of the 64-bit value from addr+4. Also make ldrexd and strexd agree that for a 64 bit value the address in env->exclusive_addr is that of the low word. This fixes the issues reported in https://bugs.launchpad.net/qemu/+bug/670883 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07target-arm: Handle 'smc' as an undefined instructionAdam Lackorzynski1-1/+8
Refine check on bkpt so that smc and undefined instruction encodings are handled as an undefined instruction and trap. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07target-arm: Fix mixup in decoding of saturating add and subJohan Bengtsson1-2/+2
The thumb2 decoder contained a mixup between the bit controlling doubling and the bit controlling if the operation was an add or a sub. Signed-off-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
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