Age | Commit message (Expand) | Author | Files | Lines |
2014-08-29 | target-arm: Implement pmccfiltr_write function | Alistair Francis | 1 | -0/+9 |
2014-08-29 | target-arm: Remove old code and replace with new functions | Alistair Francis | 1 | -23/+4 |
2014-08-29 | target-arm: Implement pmccntr_sync function | Alistair Francis | 2 | -0/+34 |
2014-08-29 | target-arm: Add arm_ccnt_enabled function | Alistair Francis | 1 | -0/+12 |
2014-08-29 | target-arm: Implement PMCCNTR_EL0 and related registers | Alistair Francis | 2 | -8/+42 |
2014-08-29 | arm: Implement PMCCNTR 32b read-modify-write | Peter Crosthwaite | 1 | -1/+10 |
2014-08-29 | target-arm: Make the ARM PMCCNTR register 64-bit | Alistair Francis | 2 | -11/+10 |
2014-08-29 | target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values | Peter Maydell | 1 | -1/+2 |
2014-08-29 | target-arm: Fix regression that disabled VFP for ARMv5 CPUs | Peter Maydell | 1 | -1/+8 |
2014-08-19 | arm: cortex-a9: Fix cache-line size and associativity | Peter Crosthwaite | 1 | -2/+2 |
2014-08-19 | arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2 | Christoffer Dall | 1 | -0/+27 |
2014-08-19 | target-arm: Rename QEMU PSCI v0.1 definitions | Christoffer Dall | 1 | -11/+11 |
2014-08-19 | target-arm: Implement MDSCR_EL1 as having state | Peter Maydell | 1 | -1/+3 |
2014-08-19 | target-arm: Implement ARMv8 single-stepping for AArch32 code | Peter Maydell | 2 | -2/+95 |
2014-08-19 | target-arm: Implement ARMv8 single-step handling for A64 code | Peter Maydell | 6 | -5/+131 |
2014-08-19 | target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb | Peter Maydell | 1 | -2/+3 |
2014-08-19 | target-arm: Set PSTATE.SS correctly on exception return from AArch64 | Peter Maydell | 2 | -0/+81 |
2014-08-19 | target-arm: Correctly handle PSTATE.SS when taking exception to AArch32 | Peter Maydell | 1 | -0/+4 |
2014-08-19 | target-arm: Don't allow AArch32 to access RES0 CPSR bits | Peter Maydell | 3 | -9/+18 |
2014-08-19 | target-arm: Adjust debug ID registers per-CPU | Peter Maydell | 4 | -7/+31 |
2014-08-19 | target-arm: Provide both 32 and 64 bit versions of debug registers | Peter Maydell | 1 | -14/+20 |
2014-08-19 | target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14 | Peter Maydell | 1 | -3/+8 |
2014-08-19 | target-arm: Collect up the debug cp register definitions | Peter Maydell | 1 | -32/+53 |
2014-08-19 | target-arm: Fix return address for A64 BRK instructions | Peter Maydell | 1 | -1/+1 |
2014-08-12 | trace: [tcg] Include TCG-tracing header on all targets | Lluís Vilanova | 2 | -0/+5 |
2014-08-04 | target-arm: A64: fix TLB flush instructions | Alex Bennée | 1 | -2/+8 |
2014-08-04 | target-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault | Alex Bennée | 1 | -2/+2 |
2014-08-04 | target-arm: Fix bit test in sp_el0_access | Stefan Weil | 1 | -1/+1 |
2014-08-04 | target-arm: Add FAR_EL2 and 3 | Edgar E. Iglesias | 2 | -1/+7 |
2014-08-04 | target-arm: Add ESR_EL2 and 3 | Edgar E. Iglesias | 2 | -1/+9 |
2014-08-04 | target-arm: Make far_el1 an array | Edgar E. Iglesias | 4 | -10/+10 |
2014-08-04 | target-arm: A64: Respect SPSEL when taking exceptions | Edgar E. Iglesias | 1 | -2/+2 |
2014-08-04 | target-arm: A64: Respect SPSEL in ERET SP restore | Edgar E. Iglesias | 1 | -1/+1 |
2014-08-04 | target-arm: A64: Break out aarch64_save/restore_sp | Edgar E. Iglesias | 3 | -24/+24 |
2014-07-08 | target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUs | Peter Maydell | 2 | -18/+5 |
2014-06-24 | Fix new typos (found by codespell) | Stefan Weil | 1 | -1/+1 |
2014-06-19 | target-arm: Introduce per-CPU field for PSCI version | Pranavkumar Sawargaonkar | 4 | -0/+9 |
2014-06-19 | target-arm: Implement kvm_arch_reset_vcpu() for KVM ARM64 | Pranavkumar Sawargaonkar | 1 | -0/+4 |
2014-06-19 | target-arm: Enable KVM_ARM_VCPU_PSCI_0_2 feature when possible | Pranavkumar Sawargaonkar | 2 | -0/+6 |
2014-06-19 | target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 | Pranavkumar Sawargaonkar | 5 | -12/+44 |
2014-06-19 | target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv() | Peter Maydell | 1 | -1/+1 |
2014-06-19 | target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int() | Peter Maydell | 1 | -1/+2 |
2014-06-19 | target-arm: Add ULL suffix to calculation of page size | Peter Maydell | 1 | -1/+1 |
2014-06-19 | target-arm: implement PD0/PD1 bits for TTBCR | Fabian Aggeler | 2 | -18/+60 |
2014-06-16 | target-arm: Use Common Tables in AES Instructions | Tom Musta | 1 | -75/+4 |
2014-06-09 | target-arm: Delete unused iwmmxt_msadb helper | Peter Maydell | 3 | -13/+0 |
2014-06-09 | target-arm: Fix errors in writes to generic timer control registers | Peter Maydell | 1 | -3/+3 |
2014-06-09 | target-arm: A64: Implement two-register SHA instructions | Peter Maydell | 1 | -1/+44 |
2014-06-09 | target-arm: A64: Implement 3-register SHA instructions | Peter Maydell | 1 | -1/+58 |
2014-06-09 | target-arm: A64: Implement AES instructions | Peter Maydell | 1 | -1/+50 |