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2014-12-11target-arm: Check error conditions on kvm_arm_reset_vcpuChristoffer Dall1-2/+11
2014-12-11target-arm: Support save/load for 64 bit CPUsPeter Maydell1-3/+19
2014-12-11target-arm/kvm: make reg sync code common between kvm32/64Alex Bennée4-101/+137
2014-12-11target-arm: make MAIR0/1 bankedGreg Bellows2-4/+29
2014-12-11target-arm: make c13 cp regs banked (FCSEIDR, ...)Fabian Aggeler3-19/+77
2014-12-11target-arm: make VBAR bankedGreg Bellows2-3/+12
2014-12-11target-arm: make PAR bankedFabian Aggeler2-11/+22
2014-12-11target-arm: make IFAR/DFAR bankedFabian Aggeler3-9/+28
2014-12-11target-arm: make DFSR bankedFabian Aggeler2-4/+13
2014-12-11target-arm: make IFSR bankedFabian Aggeler2-5/+18
2014-12-11target-arm: make DACR bankedFabian Aggeler2-12/+29
2014-12-11target-arm: make TTBCR bankedFabian Aggeler3-31/+58
2014-12-11target-arm: make TTBR0/1 bankedFabian Aggeler2-14/+43
2014-12-11target-arm: make CSSELR bankedFabian Aggeler2-4/+20
2014-12-11target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFIFabian Aggeler1-0/+54
2014-12-11target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler4-34/+58
2014-12-11target-arm: add MVBAR supportFabian Aggeler2-6/+10
2014-12-11target-arm: add SDER definitionGreg Bellows2-0/+9
2014-12-11target-arm: add NSACR registerFabian Aggeler2-0/+5
2014-12-11target-arm: implement IRQ/FIQ routing to Monitor modeFabian Aggeler1-0/+9
2014-12-11target-arm: move AArch32 SCR into security reglistFabian Aggeler1-6/+13
2014-12-11target-arm: insert AArch32 cpregs twice into hashtableFabian Aggeler1-17/+81
2014-12-11target-arm: add secure state bit to CPREG hashPeter Maydell4-16/+36
2014-12-11target-arm: add CPREG secure state supportFabian Aggeler1-2/+34
2014-12-11target-arm: add non-secure Translation Block flagSergey Fedorov3-0/+29
2014-12-11target-arm: add banked register accessorsFabian Aggeler1-0/+27
2014-12-11target-arm: add async excp target_el functionGreg Bellows1-19/+97
2014-12-11target-arm: extend async excp maskingGreg Bellows1-14/+52
2014-12-11Pass semihosting exit code back to system.Liviu Ionescu1-2/+9
2014-11-17target-arm: handle address translations that start at level 3Peter Maydell1-9/+11
2014-11-04target-arm: Correct condition for taking VIRQ and VFIQPeter Maydell1-2/+2
2014-11-04target-arm: Separate out M profile cpu_exec_interrupt handlingPeter Maydell2-24/+41
2014-11-04target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn()Peter Maydell1-6/+5
2014-11-04target-arm/translate.c: Don't pass CPUARMState around in the decoderPeter Maydell1-44/+50
2014-11-04target-arm/translate.c: Don't use IS_M()Peter Maydell1-8/+11
2014-11-04target-arm/translate.c: Use arm_dc_feature() rather than arm_feature()Peter Maydell1-60/+80
2014-11-04target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macrosPeter Maydell1-8/+8
2014-11-02target-arm: A64: remove redundant storeAlex Bennée1-1/+0
2014-10-24target-arm: A32: Emulate the SMC instructionFabian Aggeler2-2/+12
2014-10-24target-arm: make arm_current_el() return EL3Fabian Aggeler1-9/+20
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows8-47/+50
2014-10-24target-arm: reject switching to monitor modeSergey Fedorov1-0/+2
2014-10-24target-arm: add arm_is_secure() functionFabian Aggeler1-0/+47
2014-10-24target-arm: increase arrays of registers R13 & R14Fabian Aggeler2-4/+4
2014-10-24target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0Peter Maydell1-0/+3
2014-10-24target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"Peter Maydell1-1/+1
2014-10-24target-arm: Correct sense of the DCZID DZP bitPeter Maydell2-3/+3
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring9-3/+301
2014-10-24target-arm: Add support for A32 and T32 HVC and SMC insnsPeter Maydell3-11/+104
2014-10-24target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpersPeter Maydell2-9/+12
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