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AgeCommit message (Expand)AuthorFilesLines
2014-08-04target-arm: don't hardcode mask values in arm_cpu_handle_mmu_faultAlex Bennée1-2/+2
2014-08-04target-arm: Fix bit test in sp_el0_accessStefan Weil1-1/+1
2014-08-04target-arm: Add FAR_EL2 and 3Edgar E. Iglesias2-1/+7
2014-08-04target-arm: Add ESR_EL2 and 3Edgar E. Iglesias2-1/+9
2014-08-04target-arm: Make far_el1 an arrayEdgar E. Iglesias4-10/+10
2014-08-04target-arm: A64: Respect SPSEL when taking exceptionsEdgar E. Iglesias1-2/+2
2014-08-04target-arm: A64: Respect SPSEL in ERET SP restoreEdgar E. Iglesias1-1/+1
2014-08-04target-arm: A64: Break out aarch64_save/restore_spEdgar E. Iglesias3-24/+24
2014-07-08target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUsPeter Maydell2-18/+5
2014-06-24Fix new typos (found by codespell)Stefan Weil1-1/+1
2014-06-19target-arm: Introduce per-CPU field for PSCI versionPranavkumar Sawargaonkar4-0/+9
2014-06-19target-arm: Implement kvm_arch_reset_vcpu() for KVM ARM64Pranavkumar Sawargaonkar1-0/+4
2014-06-19target-arm: Enable KVM_ARM_VCPU_PSCI_0_2 feature when possiblePranavkumar Sawargaonkar2-0/+6
2014-06-19target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64Pranavkumar Sawargaonkar5-12/+44
2014-06-19target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv()Peter Maydell1-1/+1
2014-06-19target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int()Peter Maydell1-1/+2
2014-06-19target-arm: Add ULL suffix to calculation of page sizePeter Maydell1-1/+1
2014-06-19target-arm: implement PD0/PD1 bits for TTBCRFabian Aggeler2-18/+60
2014-06-16target-arm: Use Common Tables in AES InstructionsTom Musta1-75/+4
2014-06-09target-arm: Delete unused iwmmxt_msadb helperPeter Maydell3-13/+0
2014-06-09target-arm: Fix errors in writes to generic timer control registersPeter Maydell1-3/+3
2014-06-09target-arm: A64: Implement two-register SHA instructionsPeter Maydell1-1/+44
2014-06-09target-arm: A64: Implement 3-register SHA instructionsPeter Maydell1-1/+58
2014-06-09target-arm: A64: Implement AES instructionsPeter Maydell1-1/+50
2014-06-09target-arm: A32/T32: Mask CRC value in calling code, not helperPeter Maydell2-19/+16
2014-06-09target-arm: A64: Implement CRC instructionsPeter Maydell3-1/+85
2014-06-09target-arm: VFPv4 implies half-precision extensionPeter Maydell2-4/+1
2014-06-09target-arm: Clean up handling of ARMv8 optional feature bitsPeter Maydell2-4/+14
2014-06-09target-arm: Remove unnecessary setting of feature bitsPeter Maydell2-4/+0
2014-06-09target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64Peter Maydell1-3/+0
2014-06-09target-arm: A64: Use PMULL feature bit for PMULLPeter Maydell1-1/+1
2014-06-09target-arm: add support for v8 VMULL.P64 instructionPeter Maydell7-33/+60
2014-06-09target-arm: Allow 3reg_wide undefreq to encode more bad size optionsPeter Maydell1-12/+12
2014-06-09target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel5-7/+347
2014-06-09target-arm: Correct handling of UXN bit in ARMv8 LPAE page tablesIan Campbell1-9/+8
2014-06-09target-arm: Prepare cpreg writefns/readfns for EL3/SecExtFabian Aggeler1-14/+14
2014-06-09target-arm/cpu64.c: Actually register Cortex-A57 impdef registersPeter Maydell1-0/+1
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini3-4/+3
2014-06-05target-arm: move arm_*_code to a separate filePaolo Bonzini5-22/+50
2014-06-05softmmu: commonize helper definitionsPaolo Bonzini1-14/+0
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson9-16/+10
2014-05-27target-arm: A64: Register VBAR_EL3Edgar E. Iglesias2-1/+6
2014-05-27target-arm: A64: Register VBAR_EL2Edgar E. Iglesias2-1/+22
2014-05-27target-arm: Make vbar_write writeback to any CPREGEdgar E. Iglesias1-1/+1
2014-05-27target-arm: A64: Generalize update_spsel for the various ELsEdgar E. Iglesias1-5/+6
2014-05-27target-arm: A64: Generalize ERET to various ELsEdgar E. Iglesias1-5/+6
2014-05-27target-arm: A64: Trap ERET from EL0 at translation timeEdgar E. Iglesias1-0/+4
2014-05-27target-arm: A64: Forbid ERET to higher or unimplemented ELsEdgar E. Iglesias1-2/+6
2014-05-27target-arm: Register EL3 versions of ELR and SPSREdgar E. Iglesias1-0/+16
2014-05-27target-arm: Register EL2 versions of ELR and SPSREdgar E. Iglesias1-0/+16
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