| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2014-02-11 | exec: Make stl_*_phys input an AddressSpace | Edgar E. Iglesias | 1 | -1/+2 |
| 2014-02-11 | exec: Make ldq/ldub_*_phys input an AddressSpace | Edgar E. Iglesias | 1 | -1/+2 |
| 2014-02-11 | exec: Make ldl_*_phys input an AddressSpace | Edgar E. Iglesias | 1 | -6/+9 |
| 2014-02-08 | disas: Implement disassembly output for A64 | Claudio Fontana | 1 | -1/+1 |
| 2014-02-08 | target-arm: Add support for AArch32 64bit VCVTB and VCVTT | Will Newton | 1 | -22/+61 |
| 2014-02-08 | target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group | Peter Maydell | 1 | -3/+20 |
| 2014-02-08 | target-arm: A64: Add 2-reg-misc REV* instructions | Alex Bennée | 1 | -1/+70 |
| 2014-02-08 | target-arm: A64: Add narrowing 2-reg-misc instructions | Peter Maydell | 1 | -2/+83 |
| 2014-02-08 | target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT | Peter Maydell | 3 | -6/+41 |
| 2014-02-08 | target-arm: A64: Implement 2-register misc compares, ABS, NEG | Peter Maydell | 1 | -2/+134 |
| 2014-02-08 | target-arm: A64: Add skeleton decode for SIMD 2-reg misc group | Peter Maydell | 1 | -1/+109 |
| 2014-02-08 | target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc | Peter Maydell | 1 | -1/+86 |
| 2014-02-08 | target-arm: A64: Implement remaining integer scalar-3-same insns | Peter Maydell | 1 | -19/+87 |
| 2014-02-08 | target-arm: A64: Implement scalar pairwise ops | Peter Maydell | 1 | -1/+113 |
| 2014-02-08 | target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD | Peter Maydell | 1 | -1/+123 |
| 2014-02-08 | target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns | Peter Maydell | 1 | -4/+127 |
| 2014-02-08 | target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns | Peter Maydell | 1 | -22/+112 |
| 2014-01-31 | target-arm: A64: Add SIMD shift by immediate | Alex Bennée | 1 | -2/+373 |
| 2014-01-31 | target-arm: A64: Add simple SIMD 3-same floating point ops | Peter Maydell | 1 | -2/+188 |
| 2014-01-31 | target-arm: A64: Add integer ops from SIMD 3-same group | Peter Maydell | 1 | -1/+164 |
| 2014-01-31 | target-arm: A64: Add logic ops from SIMD 3 same group | Peter Maydell | 1 | -1/+72 |
| 2014-01-31 | target-arm: A64: Add top level decode for SIMD 3-same group | Peter Maydell | 1 | -1/+44 |
| 2014-01-31 | target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops | Peter Maydell | 1 | -1/+130 |
| 2014-01-31 | target-arm: A64: Add SIMD three-different ABDL instructions | Peter Maydell | 1 | -2/+33 |
| 2014-01-31 | target-arm: A64: Add SIMD three-different multiply accumulate insns | Peter Maydell | 1 | -1/+232 |
| 2014-01-31 | target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM | Will Newton | 1 | -1/+52 |
| 2014-01-31 | target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM | Will Newton | 1 | -0/+61 |
| 2014-01-31 | target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ | Will Newton | 1 | -1/+39 |
| 2014-01-31 | target-arm: Add set_neon_rmode helper | Will Newton | 2 | -0/+18 |
| 2014-01-31 | target-arm: Add support for AArch32 SIMD VRINTX | Will Newton | 1 | -1/+10 |
| 2014-01-31 | target-arm: Add support for AArch32 FP VRINTX | Will Newton | 1 | -0/+11 |
| 2014-01-31 | target-arm: Add support for AArch32 FP VRINTZ | Will Newton | 1 | -0/+16 |
| 2014-01-31 | target-arm: Add support for AArch32 FP VRINTR | Will Newton | 1 | -0/+11 |
| 2014-01-31 | target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM | Will Newton | 1 | -0/+54 |
| 2014-01-31 | target-arm: Move arm_rmode_to_sf to a shared location. | Will Newton | 3 | -28/+30 |
| 2014-01-31 | ARM: Convert MIDR to a property | Alistair Francis | 1 | -0/+1 |
| 2014-01-31 | target-arm: A64: Add SIMD scalar copy instructions | Peter Maydell | 1 | -1/+42 |
| 2014-01-31 | target-arm: A64: Add SIMD modified immediate group | Alex Bennée | 1 | -1/+119 |
| 2014-01-31 | target-arm: A64: Add SIMD copy operations | Alex Bennée | 1 | -1/+209 |
| 2014-01-31 | target-arm: A64: Add SIMD across-lanes instructions | Michael Matz | 1 | -1/+176 |
| 2014-01-31 | target-arm: A64: Add SIMD ZIP/UZP/TRN | Michael Matz | 1 | -1/+75 |
| 2014-01-31 | target-arm: A64: Add SIMD TBL/TBLX | Michael Matz | 3 | -1/+86 |
| 2014-01-31 | target-arm: A64: Add SIMD EXT | Peter Maydell | 1 | -1/+78 |
| 2014-01-31 | target-arm: A64: Add decode skeleton for SIMD data processing insns | Alex Bennée | 1 | -1/+305 |
| 2014-01-31 | target-arm: A64: Add SIMD ld/st single | Peter Maydell | 1 | -2/+142 |
| 2014-01-31 | target-arm: A64: Add SIMD ld/st multiple | Alex Bennée | 1 | -2/+248 |
| 2014-01-14 | Merge remote branch 'luiz/queue/qmp' into qmpq | Edgar E. Iglesias | 1 | -5/+2 |
| 2014-01-14 | target-arm: Switch ARMCPUInfo arrays to use terminator entries | Peter Maydell | 2 | -12/+12 |
| 2014-01-12 | arm: fix compile on bigendian host | Alexey Kardashevskiy | 1 | -1/+1 |
| 2014-01-08 | target-arm: A64: Add support for FCVT between half, single and double | Peter Maydell | 3 | -1/+96 |
