Age | Commit message (Expand) | Author | Files | Lines |
2014-05-28 | tcg: Invert the inclusion of helper.h | Richard Henderson | 9 | -16/+10 |
2014-05-27 | target-arm: A64: Register VBAR_EL3 | Edgar E. Iglesias | 2 | -1/+6 |
2014-05-27 | target-arm: A64: Register VBAR_EL2 | Edgar E. Iglesias | 2 | -1/+22 |
2014-05-27 | target-arm: Make vbar_write writeback to any CPREG | Edgar E. Iglesias | 1 | -1/+1 |
2014-05-27 | target-arm: A64: Generalize update_spsel for the various ELs | Edgar E. Iglesias | 1 | -5/+6 |
2014-05-27 | target-arm: A64: Generalize ERET to various ELs | Edgar E. Iglesias | 1 | -5/+6 |
2014-05-27 | target-arm: A64: Trap ERET from EL0 at translation time | Edgar E. Iglesias | 1 | -0/+4 |
2014-05-27 | target-arm: A64: Forbid ERET to higher or unimplemented ELs | Edgar E. Iglesias | 1 | -2/+6 |
2014-05-27 | target-arm: Register EL3 versions of ELR and SPSR | Edgar E. Iglesias | 1 | -0/+16 |
2014-05-27 | target-arm: Register EL2 versions of ELR and SPSR | Edgar E. Iglesias | 1 | -0/+16 |
2014-05-27 | target-arm: Add a feature flag for EL3 | Edgar E. Iglesias | 1 | -0/+1 |
2014-05-27 | target-arm: Add a feature flag for EL2 | Edgar E. Iglesias | 1 | -0/+1 |
2014-05-27 | target-arm: A64: Introduce aarch64_banked_spsr_index() | Edgar E. Iglesias | 3 | -2/+17 |
2014-05-27 | target-arm: Add SPSR entries for EL2/HYP and EL3/MON | Edgar E. Iglesias | 4 | -6/+12 |
2014-05-27 | target-arm: A64: Add ELR entries for EL2 and 3 | Edgar E. Iglesias | 2 | -4/+4 |
2014-05-27 | target-arm: A64: Add SP entries for EL2 and 3 | Edgar E. Iglesias | 2 | -4/+4 |
2014-05-27 | target-arm: c12_vbar -> vbar_el[] | Edgar E. Iglesias | 3 | -5/+5 |
2014-05-27 | target-arm: Make esr_el1 an array | Edgar E. Iglesias | 3 | -8/+8 |
2014-05-27 | target-arm: Make elr_el1 an array | Edgar E. Iglesias | 6 | -10/+11 |
2014-05-27 | target-arm: Use a 1:1 mapping between EL and MMU index | Edgar E. Iglesias | 2 | -9/+5 |
2014-05-27 | target-arm: A32: Use get_mem_index for load/stores | Edgar E. Iglesias | 1 | -106/+106 |
2014-05-27 | target-arm/translate.c: Use get_mem_index() for SRS memory accesses | Peter Maydell | 1 | -2/+2 |
2014-05-27 | target-arm/translate.c: Clean up mmu index handling for ldrt/strt | Peter Maydell | 1 | -12/+17 |
2014-05-27 | target-arm: Move get_mem_index to translate.h | Edgar E. Iglesias | 2 | -9/+9 |
2014-05-27 | target-arm: implement CPACR register logic for ARMv7 | Fabian Aggeler | 1 | -4/+28 |
2014-05-27 | target-arm: Fix segfault on startup when KVM enabled | Christoffer Dall | 1 | -1/+1 |
2014-05-15 | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140513'... | Peter Maydell | 2 | -5/+7 |
2014-05-13 | target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchanged | Peter Maydell | 1 | -0/+7 |
2014-05-13 | savevm: Remove all the unneeded version_minimum_id_old (arm) | Juan Quintela | 1 | -5/+0 |
2014-05-13 | kvm: reset state from the CPU's reset method | Paolo Bonzini | 4 | -4/+17 |
2014-05-05 | vmstate: s/VMSTATE_INT32_LE/VMSTATE_INT32_POSITIVE_LE/ | Michael S. Tsirkin | 1 | -1/+1 |
2014-05-01 | target-arm: Correct a comment refering to EL0 | Edgar E. Iglesias | 1 | -1/+1 |
2014-05-01 | target-arm: A64: Fix a typo when declaring TLBI ops | Edgar E. Iglesias | 1 | -12/+12 |
2014-05-01 | target-arm: A64: Handle blr lr | Edgar E. Iglesias | 1 | -1/+2 |
2014-05-01 | target-arm: Make vbar_write 64bit friendly on 32bit hosts | Edgar E. Iglesias | 1 | -1/+1 |
2014-05-01 | target-arm: implement WFE/YIELD as a yield for AArch64 | Rob Herring | 1 | -0/+6 |
2014-05-01 | target-arm: Implement XScale cache lockdown operations as NOPs | Peter Maydell | 1 | -0/+15 |
2014-04-17 | target-arm: A64: fix unallocated test of scalar SQXTUN | Alex Bennée | 1 | -1/+1 |
2014-04-17 | arm: translate.c: Fix smlald Instruction | Peter Crosthwaite | 1 | -11/+23 |
2014-04-17 | target-arm/gdbstub64.c: remove useless 'break' statement. | Chen Gang | 1 | -2/+0 |
2014-04-17 | target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 | Peter Maydell | 4 | -3/+13 |
2014-04-17 | target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc | Peter Maydell | 1 | -4/+8 |
2014-04-17 | target-arm: Make Cortex-A15 CBAR read-only | Peter Maydell | 1 | -1/+1 |
2014-04-17 | target-arm: Implement CBAR for Cortex-A57 | Peter Maydell | 5 | -9/+42 |
2014-04-17 | target-arm: Implement Cortex-A57 implementation-defined system registers | Peter Maydell | 1 | -0/+55 |
2014-04-17 | target-arm: Implement RVBAR register | Peter Maydell | 3 | -0/+16 |
2014-04-17 | target-arm: Implement AArch64 address translation operations | Peter Maydell | 2 | -31/+25 |
2014-04-17 | target-arm: Implement auxiliary fault status registers | Peter Maydell | 1 | -0/+9 |
2014-04-17 | target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8 | Peter Maydell | 1 | -5/+91 |
2014-04-17 | target-arm: Don't expose wildcard ID register definitions for ARMv8 | Peter Maydell | 1 | -18/+43 |