index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-arm
Age
Commit message (
Expand
)
Author
Files
Lines
2014-01-14
Merge remote branch 'luiz/queue/qmp' into qmpq
Edgar E. Iglesias
1
-5
/
+2
2014-01-14
target-arm: Switch ARMCPUInfo arrays to use terminator entries
Peter Maydell
2
-12
/
+12
2014-01-12
arm: fix compile on bigendian host
Alexey Kardashevskiy
1
-1
/
+1
2014-01-08
target-arm: A64: Add support for FCVT between half, single and double
Peter Maydell
3
-1
/
+96
2014-01-08
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
Peter Maydell
3
-1
/
+191
2014-01-08
target-arm: A64: Add floating-point<->integer conversion instructions
Will Newton
1
-3
/
+20
2014-01-08
target-arm: A64: Add floating-point<->fixed-point instructions
Alexander Graf
3
-1
/
+200
2014-01-08
target-arm: A64: Add extra VFP fixed point conversion helpers
Will Newton
2
-1
/
+26
2014-01-08
target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion
Peter Maydell
1
-0
/
+9
2014-01-08
target-arm: Rename A32 VFP conversion helpers
Will Newton
3
-24
/
+35
2014-01-08
target-arm: Prepare VFP_CONV_FIX helpers for A64 uses
Will Newton
1
-14
/
+14
2014-01-08
target-arm: fix build with gcc 4.8.2
Michael S. Tsirkin
1
-0
/
+6
2014-01-08
target-arm: remove raw_read|write duplication
Peter Crosthwaite
1
-10
/
+2
2014-01-08
target-arm: use c13_context field for CONTEXTIDR
Sergey Fedorov
1
-1
/
+1
2014-01-08
target-arm: Give the FPSCR rounding modes names
Alexander Graf
2
-4
/
+13
2014-01-08
target-arm: A64: Add support for floating point cond select
Claudio Fontana
1
-1
/
+44
2014-01-08
target-arm: A64: Add support for floating point conditional compare
Claudio Fontana
1
-1
/
+34
2014-01-08
target-arm: A64: Add support for floating point compare
Claudio Fontana
3
-1
/
+113
2014-01-08
target-arm: A64: Add fmov (scalar, immediate) instruction
Alexander Graf
1
-1
/
+31
2014-01-08
target-arm: A64: Add "Floating-point data-processing (3 source)" insns
Alexander Graf
1
-1
/
+94
2014-01-08
target-arm: A64: Add "Floating-point data-processing (2 source)" insns
Alexander Graf
1
-1
/
+181
2014-01-08
target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum
Peter Maydell
4
-52
/
+20
2014-01-08
target-arm: A64: Fix vector register access on bigendian hosts
Peter Maydell
1
-34
/
+35
2014-01-08
target-arm: A64: Add support for dumping AArch64 VFP register state
Alexander Graf
1
-0
/
+16
2014-01-08
target-arm: A64: support for ld/st/cl exclusive
Michael Matz
1
-3
/
+153
2014-01-08
target-arm: Widen exclusive-access support struct fields to 64 bits
Peter Maydell
3
-36
/
+49
2014-01-08
target-arm: aarch64: add support for ld lit
Alexander Graf
1
-2
/
+45
2014-01-08
target-arm: A64: add support for conditional compare insns
Claudio Fontana
1
-13
/
+60
2014-01-08
target-arm: A64: add support for add/sub with carry
Claudio Fontana
1
-2
/
+103
2014-01-07
target-arm: Widen thread-local register state fields to 64 bits
Peter Maydell
2
-10
/
+30
2014-01-07
target-arm: A64: Implement minimal set of EL0-visible sysregs
Peter Maydell
3
-1
/
+115
2014-01-07
target-arm: A64: Implement MRS/MSR/SYS/SYSL
Peter Maydell
1
-30
/
+82
2014-01-07
target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
Peter Maydell
5
-12
/
+17
2014-01-06
hw: Remove assert_no_error usages
Peter Crosthwaite
1
-5
/
+2
2014-01-04
target-arm: Update generic cpreg code for AArch64
Peter Maydell
3
-9
/
+211
2014-01-04
target-arm: Pull "add one cpreg to hashtable" into its own function
Peter Maydell
1
-42
/
+52
2013-12-23
target-arm: A64: implement FMOV
Peter Maydell
1
-1
/
+85
2013-12-23
target-arm: A64: Add decoder skeleton for FP instructions
Peter Maydell
1
-1
/
+169
2013-12-23
target-arm: A64: implement SVC, BRK
Alexander Graf
1
-2
/
+49
2013-12-23
target-arm: A64: add support for 3 src data proc insns
Alexander Graf
1
-2
/
+95
2013-12-23
target-arm: A64: add support for move wide instructions
Alex Bennée
1
-2
/
+49
2013-12-23
target-arm: A64: add support for add, addi, sub, subi
Alex Bennée
1
-6
/
+286
2013-12-23
target-arm: A64: add support for ld/st with index
Alex Bennée
1
-1
/
+124
2013-12-23
target-arm: A64: add support for ld/st with reg offset
Alex Bennée
1
-1
/
+143
2013-12-23
target-arm: A64: add support for ld/st unsigned imm
Alex Bennée
1
-1
/
+88
2013-12-23
target-arm: A64: add support for ld/st pair
Peter Maydell
1
-2
/
+277
2013-12-17
target-arm: A64: add support for logical (immediate) insns
Alexander Graf
1
-2
/
+173
2013-12-17
target-arm: A64: add support for 1-src CLS insn
Claudio Fontana
3
-1
/
+31
2013-12-17
target-arm: A64: add support for bitfield insns
Claudio Fontana
1
-2
/
+54
2013-12-17
target-arm: A64: add support for 1-src REV insns
Claudio Fontana
1
-1
/
+72
[next]