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target-arm
Age
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Author
Files
Lines
2014-10-24
target-arm: reject switching to monitor mode
Sergey Fedorov
1
-0
/
+2
2014-10-24
target-arm: add arm_is_secure() function
Fabian Aggeler
1
-0
/
+47
2014-10-24
target-arm: increase arrays of registers R13 & R14
Fabian Aggeler
2
-4
/
+4
2014-10-24
target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0
Peter Maydell
1
-0
/
+3
2014-10-24
target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"
Peter Maydell
1
-1
/
+1
2014-10-24
target-arm: Correct sense of the DCZID DZP bit
Peter Maydell
2
-3
/
+3
2014-10-24
target-arm: add emulation of PSCI calls for system emulation
Rob Herring
9
-3
/
+301
2014-10-24
target-arm: Add support for A32 and T32 HVC and SMC insns
Peter Maydell
3
-11
/
+104
2014-10-24
target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers
Peter Maydell
2
-9
/
+12
2014-10-24
target-arm: add missing PSCI constants needed for PSCI emulation
Ard Biesheuvel
1
-0
/
+40
2014-10-24
target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes
Rob Herring
4
-6
/
+6
2014-10-24
target-arm: add powered off cpu state
Rob Herring
3
-3
/
+12
2014-10-06
gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flag
Peter Maydell
1
-0
/
+1
2014-09-29
target-arm: Add support for VIRQ and VFIQ
Edgar E. Iglesias
5
-14
/
+76
2014-09-29
target-arm: Add IRQ and FIQ routing to EL2 and 3
Edgar E. Iglesias
2
-0
/
+27
2014-09-29
target-arm: A64: Emulate the SMC insn
Edgar E. Iglesias
7
-0
/
+51
2014-09-29
target-arm: Add a Hypervisor Trap exception type
Edgar E. Iglesias
4
-0
/
+4
2014-09-29
target-arm: A64: Emulate the HVC insn
Edgar E. Iglesias
7
-10
/
+81
2014-09-29
target-arm: A64: Correct updates to FAR and ESR on exceptions
Edgar E. Iglesias
1
-4
/
+3
2014-09-29
target-arm: Don't take interrupts targeting lower ELs
Edgar E. Iglesias
1
-0
/
+7
2014-09-29
target-arm: Break out exception masking to a separate func
Edgar E. Iglesias
2
-5
/
+17
2014-09-29
target-arm: A64: Refactor aarch64_cpu_do_interrupt
Edgar E. Iglesias
3
-11
/
+33
2014-09-29
target-arm: Add SCR_EL3
Edgar E. Iglesias
2
-3
/
+51
2014-09-29
target-arm: Add HCR_EL2
Edgar E. Iglesias
2
-0
/
+70
2014-09-29
target-arm: Don't handle c15_cpar changes via tb_flush()
Peter Maydell
6
-30
/
+44
2014-09-29
target-arm: Implement handling of breakpoint firing
Peter Maydell
2
-15
/
+66
2014-09-29
target-arm: Implement setting guest breakpoints
Peter Maydell
5
-2
/
+136
2014-09-25
target-arm: Use cpu_exec_interrupt qom hook
Richard Henderson
3
-0
/
+36
2014-09-12
target-arm: Make *IS TLB maintenance ops affect all CPUs
Peter Maydell
1
-12
/
+89
2014-09-12
target-arm: Push legacy wildcard TLB ops back into v6
Peter Maydell
1
-47
/
+55
2014-09-12
target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0
Peter Maydell
1
-0
/
+19
2014-09-12
target-arm: Remove comment about MDSCR_EL1 being dummy implementation
Peter Maydell
1
-3
/
+1
2014-09-12
target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32
Peter Maydell
1
-0
/
+26
2014-09-12
target-arm: Implement handling of fired watchpoints
Peter Maydell
4
-1
/
+204
2014-09-12
target-arm: Move extended_addresses_enabled() to internals.h
Peter Maydell
2
-11
/
+11
2014-09-12
target-arm: Implement setting of watchpoints
Peter Maydell
5
-3
/
+149
2014-09-12
target-arm: Fix broken indentation in arm_cpu_reest()
Martin Galvan
1
-1
/
+1
2014-09-12
target-arm: Fix resetting issues on ARMv7-M CPUs
Martin Galvan
1
-10
/
+22
2014-08-29
target-arm: Implement pmccfiltr_write function
Alistair Francis
1
-0
/
+9
2014-08-29
target-arm: Remove old code and replace with new functions
Alistair Francis
1
-23
/
+4
2014-08-29
target-arm: Implement pmccntr_sync function
Alistair Francis
2
-0
/
+34
2014-08-29
target-arm: Add arm_ccnt_enabled function
Alistair Francis
1
-0
/
+12
2014-08-29
target-arm: Implement PMCCNTR_EL0 and related registers
Alistair Francis
2
-8
/
+42
2014-08-29
arm: Implement PMCCNTR 32b read-modify-write
Peter Crosthwaite
1
-1
/
+10
2014-08-29
target-arm: Make the ARM PMCCNTR register 64-bit
Alistair Francis
2
-11
/
+10
2014-08-29
target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values
Peter Maydell
1
-1
/
+2
2014-08-29
target-arm: Fix regression that disabled VFP for ARMv5 CPUs
Peter Maydell
1
-1
/
+8
2014-08-19
arm: cortex-a9: Fix cache-line size and associativity
Peter Crosthwaite
1
-2
/
+2
2014-08-19
arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2
Christoffer Dall
1
-0
/
+27
2014-08-19
target-arm: Rename QEMU PSCI v0.1 definitions
Christoffer Dall
1
-11
/
+11
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