aboutsummaryrefslogtreecommitdiff
path: root/target-arm
AgeCommit message (Expand)AuthorFilesLines
2015-09-15target-arm: Use new revbit functionsRichard Henderson2-25/+2
2015-09-14target-arm: Add VMPIDR_EL2Edgar E. Iglesias2-2/+25
2015-09-14target-arm: Break out mpidr_read_val()Edgar E. Iglesias1-1/+6
2015-09-14target-arm: Add VPIDR_EL2Edgar E. Iglesias2-1/+42
2015-09-14target-arm: Suppress EPD for S2, EL2 and EL3 translationsEdgar E. Iglesias1-2/+4
2015-09-14target-arm: Suppress TBI for S2 translationsEdgar E. Iglesias1-1/+3
2015-09-14target-arm: Add VTTBR_EL2Edgar E. Iglesias2-2/+33
2015-09-14target-arm: Add VTCR_EL2Edgar E. Iglesias2-2/+42
2015-09-14target-arm: Use tcg_gen_extrh_i64_i32Richard Henderson1-25/+9
2015-09-14target-arm: Recognize RORRichard Henderson1-12/+21
2015-09-14target-arm: Eliminate unnecessary zero-extend in disas_bitfieldRichard Henderson1-1/+5
2015-09-14target-arm: Recognize UXTB, UXTH, LSR, LSLRichard Henderson1-0/+17
2015-09-14target-arm: Recognize SXTB, SXTH, SXTW, ASRRichard Henderson1-1/+23
2015-09-14target-arm: Implement fcsel with movcondRichard Henderson1-28/+17
2015-09-14target-arm: Implement ccmp branchlessRichard Henderson1-16/+58
2015-09-14target-arm: Use setcond and movcond for cselRichard Henderson1-36/+49
2015-09-14target-arm: Handle always condition codes within arm_test_ccRichard Henderson1-0/+9
2015-09-14target-arm: Introduce DisasCompareRichard Henderson2-46/+78
2015-09-14target-arm: Share all common TCG temporariesRichard Henderson3-27/+13
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2-4/+4
2015-09-11typofixes - v4Veres Lajos1-2/+2
2015-09-11maint: remove / fix many doubled wordsDaniel P. Berrange3-4/+4
2015-09-08target-arm: Add AArch64 access to PAR_EL1Edgar E. Iglesias1-0/+6
2015-09-08target-arm: Correct opc1 for AT_S12ExxEdgar E. Iglesias1-4/+4
2015-09-08target-arm: Log the target EL when taking exceptionsEdgar E. Iglesias1-1/+2
2015-09-08target-arm: Fix default_exception_el() function for the case when EL3 is not ...Sergey Sorokin3-4/+13
2015-09-07target-arm: Refactor CPU affinity handlingPavel Fedin4-5/+16
2015-09-07target-arm: Fix arm_excp_unmasked() functionSergey Sorokin1-3/+3
2015-09-07target-arm: Fix AArch32:AArch64 general-purpose register mappingSergey Sorokin1-32/+32
2015-09-07arm: Remove hw_error() usages.Peter Crosthwaite2-3/+3
2015-09-07arm: cpu: assert() on no-EL2 virt IRQ error condition.Peter Crosthwaite1-4/+1
2015-09-07target-arm: Wire up HLT 0xf000 as the A64 semihosting instructionPeter Maydell4-2/+31
2015-09-07target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter blockPeter Maydell1-3/+18
2015-09-07target-arm/arm-semi.c: Implement A64 specific SyncCacheRange callPeter Maydell1-0/+10
2015-09-07target-arm/arm-semi.c: Support widening APIs to 64 bitsPeter Maydell2-13/+58
2015-09-07target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'Peter Maydell1-32/+47
2015-09-07target-arm: Improve semihosting debug printsChristopher Covington1-3/+9
2015-09-07target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdbPeter Maydell1-1/+1
2015-08-25target-arm: Implement AArch64 TLBI operations on IPAsPeter Maydell1-0/+55
2015-08-25target-arm: Implement missing EL3 TLB invalidate operationsPeter Maydell1-0/+76
2015-08-25target-arm: Implement missing EL2 TLBI operationsPeter Maydell1-0/+22
2015-08-25target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touchPeter Maydell1-43/+129
2015-08-25target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric orderPeter Maydell1-8/+8
2015-08-25target-arm: Implement AArch32 ATS1H* operationsPeter Maydell1-0/+22
2015-08-25target-arm: Enable the AArch32 ATS12NSO opsPeter Maydell1-5/+11
2015-08-25target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3Peter Maydell2-0/+11
2015-08-25target-arm: Wire up AArch64 EL2 and EL3 address translation opsPeter Maydell1-2/+41
2015-08-25target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translationsPeter Maydell1-0/+5
2015-08-25target-arm: Implement missing ACTLR registersPeter Maydell1-6/+15
2015-08-25target-arm: Implement missing AFSR registersPeter Maydell1-0/+24
generated by cgit v1.1 at 2024-12-25 13:28:40 +0000