index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-arm
/
translate.h
Age
Commit message (
Expand
)
Author
Files
Lines
2016-03-04
target-arm: introduce disas flag for endianness
Paolo Bonzini
1
-0
/
+1
2016-03-04
target-arm: implement SCTLR.B, drop bswap_code
Paolo Bonzini
1
-1
/
+1
2016-03-01
tcg: Add type for vCPU pointers
LluĂs Vilanova
1
-1
/
+1
2015-10-07
tcg: Remove gen_intermediate_code_pc
Richard Henderson
1
-6
/
+2
2015-09-14
target-arm: Introduce DisasCompare
Richard Henderson
1
-0
/
+9
2015-09-14
target-arm: Share all common TCG temporaries
Richard Henderson
1
-0
/
+8
2015-09-08
target-arm: Fix default_exception_el() function for the case when EL3 is not ...
Sergey Sorokin
1
-2
/
+3
2015-07-06
target-arm: Split DISAS_YIELD from DISAS_WFE
Peter Maydell
1
-0
/
+1
2015-05-29
target-arm: Extend FP checks to use an EL
Greg Bellows
1
-1
/
+1
2015-05-29
target-arm: Add exception target el infrastructure
Greg Bellows
1
-0
/
+15
2015-03-13
tcg: Change translator-side labels to a pointer
Richard Henderson
1
-2
/
+2
2015-02-05
target-arm: Define correct mmu_idx values and pass them in TB flags
Peter Maydell
1
-1
/
+2
2014-12-11
target-arm: add non-secure Translation Block flag
Sergey Fedorov
1
-0
/
+1
2014-10-24
target-arm: rename arm_current_pl to arm_current_el
Greg Bellows
1
-2
/
+2
2014-10-24
target-arm: Add support for A32 and T32 HVC and SMC insns
Peter Maydell
1
-0
/
+2
2014-09-29
target-arm: Don't handle c15_cpar changes via tb_flush()
Peter Maydell
1
-0
/
+2
2014-08-19
target-arm: Implement ARMv8 single-step handling for A64 code
Peter Maydell
1
-0
/
+12
2014-05-27
target-arm: Use a 1:1 mapping between EL and MMU index
Edgar E. Iglesias
1
-5
/
+1
2014-05-27
target-arm: Move get_mem_index to translate.h
Edgar E. Iglesias
1
-0
/
+9
2014-04-17
target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32
Peter Maydell
1
-0
/
+8
2014-04-17
target-arm: A64: Add assertion that FP access was checked
Peter Maydell
1
-0
/
+8
2014-04-17
target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set
Peter Maydell
1
-1
/
+2
2014-04-17
target-arm: Add support for generating exceptions with syndrome information
Peter Maydell
1
-0
/
+4
2014-03-17
target-arm: A64: Implement PMULL instruction
Peter Maydell
1
-0
/
+6
2014-03-10
target-arm: Implement WFE as a yield operation
Peter Maydell
1
-0
/
+2
2014-01-07
target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
Peter Maydell
1
-0
/
+2
2013-12-17
target-arm: A64: add support for conditional branches
Alexander Graf
1
-0
/
+2
2013-12-17
target-arm: A64: add support for B and BL insns
Alexander Graf
1
-0
/
+3
2013-12-17
target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()
Peter Maydell
1
-2
/
+18
2013-09-10
target-arm: Add AArch64 translation stub
Alexander Graf
1
-0
/
+19
2013-09-10
target-arm: Prepare translation for AArch64 code
Alexander Graf
1
-0
/
+1
2013-09-10
target-arm: Export cpu_env
Alexander Graf
1
-0
/
+2
2013-09-10
target-arm: Extract the disas struct to a header file
Alexander Graf
1
-0
/
+27