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path: root/target-arm/translate.c
AgeCommit message (Expand)AuthorFilesLines
2011-01-14target-arm: Restore IT bits when resuming after an exceptionPeter Maydell1-0/+36
2011-01-14target-arm: Refactor translation of exception generating instructionsPeter Maydell1-28/+15
2011-01-14target-arm: Remove redundant setting of IT bits before Thumb SWIPeter Maydell1-1/+0
2011-01-14target-arm: Translate with user-state from TB flags, not CPUStatePeter Maydell1-5/+1
2011-01-14target-arm: Translate with condexec bits from TB flags, not CPUStatePeter Maydell1-3/+3
2011-01-14target-arm: Translate with Thumb state from TB flags, not CPUStatePeter Maydell1-3/+3
2011-01-14target-arm: Translate with VFP len/stride from TB flags, not CPUStatePeter Maydell1-3/+7
2011-01-14target-arm: Translate with VFP-enabled from TB flags, not CPUStatePeter Maydell1-9/+5
2011-01-14target-arm: Don't generate code specific to current CPU mode for SRSPeter Maydell1-31/+15
2011-01-12ARM: Fix decoding of VQSHL/VQSHLU immediate formsPeter Maydell1-15/+36
2011-01-06target-arm: fix SMMLA/SMMLS instructionsAurelien Jarno1-45/+51
2010-12-31target-arm: fix UMAAL instructionAurelien Jarno1-10/+22
2010-12-27target-arm: Fix arguments passed to VQSHL helpersJuha Riihimäki1-2/+2
2010-12-27target-arm: fix bug in translation of REVSHAurelien Jarno1-7/+3
2010-12-07ARM: Fix sense of to_integer bit in Neon VCVT float/int conversionPeter Maydell1-4/+4
2010-12-07ARM: Fix decoding of Neon forms of VCVT between float and fixed pointPeter Maydell1-2/+6
2010-12-07ARM: Fix decoding of VFP forms of VCVT between float and int/fixedPeter Maydell1-7/+12
2010-12-07ARM: fix ldrexd/strexdPeter Maydell1-3/+5
2010-12-07target-arm: Handle 'smc' as an undefined instructionAdam Lackorzynski1-1/+8
2010-12-07target-arm: Fix mixup in decoding of saturating add and subJohan Bengtsson1-2/+2
2010-12-07target-arm: Add support for PKHxx in thumb2Johan Bengtsson1-18/+45
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil1-2/+1
2010-07-01target-arm : fix thumb2 parallel add/sub opcode decodingChih-Min Chao1-2/+2
2010-06-11NEON vldN optimizationPaul Brook1-2/+4
2010-04-25arm: remove dead assignments, spotted by clang analyzerBlue Swirl1-1/+0
2010-04-08target-arm: fix neon vmon/vmvn with modified immediateJuha Riihimäki1-1/+1
2010-04-08target-arm: resource leak fixes for iwmmxt disassembleLars Munch1-0/+2
2010-03-23target-arm: Fix handling of AL condition in IT instructionJohan Bengtsson1-3/+5
2010-03-13target-arm: make RFE usable with any registerAdam Lackorzynski1-1/+1
2010-03-06target-arm: Fix missing 'return' in SRS handling.Adam Lackorzynski1-0/+1
2010-02-28target-arm: neon vshll instruction fixJuha Riihimäki1-0/+1
2010-02-28target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHNRiku Voipio1-2/+2
2010-02-23ARM CP15 tls fixPaul Brook1-9/+7
2010-02-19target-arm: implement Thumb-2 exception returnRabin Vincent1-2/+10
2010-02-19target-arm: fix thumb CPSRabin Vincent1-1/+1
2010-02-06target-arm: refactor cp15.c13 register accessRiku Voipio1-0/+55
2009-12-24target-arm: fix strexdAurelien Jarno1-1/+1
2009-11-22ARM atomic ops rewritePaul Brook1-85/+165
2009-11-19ARM FP16 supportPaul Brook1-0/+85
2009-10-27target-arm: use native tcg-ops for ror/bic/vornAurelien Jarno1-38/+14
2009-10-27target-arm: fix neon vsri, vshl and vsli opsJuha Riihimäki1-14/+18
2009-10-27target-arm: allow modifying vfp fpexc en bit onlyJuha Riihimäki1-0/+3
2009-10-27target-arm: add support for neon vld1.64/vst1.64 instructionsJuha Riihimäki1-52/+81
2009-10-27target-arm: fix neon vshrn/vrshrn opsJuha Riihimäki1-9/+3
2009-10-26target-arm: fix incorrect temporary variable freeingJuha Riihimäki1-2/+2
2009-10-23target-arm: optimize thumb 32-bit multiplyJuha.Riihimaki@nokia.com1-17/+1
2009-10-23target-arm: cleanup internal resource leaksJuha Riihimäki1-27/+89
2009-10-18target-arm: fix bugs introduced by 1b2b1e547bd912b7d3c4863d0a0f75f6f38330edAurelien Jarno1-5/+7
2009-10-18target-arm: fix bugs introduced by 3174f8e91fecf8756e861d1febb049f3c619a2c7Aurelien Jarno1-3/+3
2009-10-17target-arm: remove cpu_T for ARM once and for allFilip Navara1-26/+0
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