| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2014-03-10 | target-arm: Implement WFE as a yield operation | Peter Maydell | 1 | -0/+6 |
| 2014-02-26 | target-arm: Add support for AArch32 ARMv8 CRC32 instructions | Will Newton | 1 | -0/+56 |
| 2014-02-20 | target-arm: Remove unnecessary code now read/write fns can't fail | Peter Maydell | 1 | -4/+0 |
| 2014-02-20 | target-arm: Split cpreg access checks out from read/write functions | Peter Maydell | 1 | -0/+11 |
| 2014-02-20 | target-arm: Log bad system register accesses with LOG_UNIMP | Peter Maydell | 1 | -0/+13 |
| 2014-02-08 | target-arm: Add support for AArch32 64bit VCVTB and VCVTT | Will Newton | 1 | -22/+61 |
| 2014-01-31 | target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM | Will Newton | 1 | -1/+52 |
| 2014-01-31 | target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM | Will Newton | 1 | -0/+61 |
| 2014-01-31 | target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ | Will Newton | 1 | -1/+39 |
| 2014-01-31 | target-arm: Add support for AArch32 SIMD VRINTX | Will Newton | 1 | -1/+10 |
| 2014-01-31 | target-arm: Add support for AArch32 FP VRINTX | Will Newton | 1 | -0/+11 |
| 2014-01-31 | target-arm: Add support for AArch32 FP VRINTZ | Will Newton | 1 | -0/+16 |
| 2014-01-31 | target-arm: Add support for AArch32 FP VRINTR | Will Newton | 1 | -0/+11 |
| 2014-01-31 | target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM | Will Newton | 1 | -0/+54 |
| 2014-01-08 | target-arm: Rename A32 VFP conversion helpers | Will Newton | 1 | -11/+13 |
| 2014-01-08 | target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum | Peter Maydell | 1 | -8/+8 |
| 2014-01-08 | target-arm: Widen exclusive-access support struct fields to 64 bits | Peter Maydell | 1 | -26/+39 |
| 2014-01-07 | target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder | Peter Maydell | 1 | -3/+4 |
| 2013-12-17 | target-arm: A64: add support for conditional branches | Alexander Graf | 1 | -5/+9 |
| 2013-12-17 | target-arm: Split A64 from A32/T32 gen_intermediate_code_internal() | Peter Maydell | 1 | -38/+24 |
| 2013-12-17 | target-arm: add support for v8 AES instructions | Ard Biesheuvel | 1 | -0/+26 |
| 2013-12-10 | target-arm: Use new qemu_ld/st opcodes | Richard Henderson | 1 | -31/+25 |
| 2013-12-10 | target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions. | Will Newton | 1 | -9/+22 |
| 2013-12-10 | target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions. | Will Newton | 1 | -0/+50 |
| 2013-12-10 | target-arm: Implement ARMv8 VSEL instruction. | Will Newton | 1 | -1/+134 |
| 2013-12-10 | target-arm: Move call to disas_vfp_insn out of disas_coproc_insn. | Will Newton | 1 | -5/+27 |
| 2013-10-10 | tcg: Move helper registration into tcg_context_init | Richard Henderson | 1 | -3/+0 |
| 2013-09-10 | target-arm: Add AArch64 translation stub | Alexander Graf | 1 | -3/+11 |
| 2013-09-10 | target-arm: Prepare translation for AArch64 code | Alexander Graf | 1 | -9/+29 |
| 2013-09-10 | target-arm: Pass DisasContext* to gen_set_pc_im() | Peter Maydell | 1 | -13/+13 |
| 2013-09-10 | target-arm: Fix target_ulong/uint32_t confusions | Alexander Graf | 1 | -4/+5 |
| 2013-09-10 | target-arm: Export cpu_env | Alexander Graf | 1 | -1/+1 |
| 2013-09-10 | target-arm: Extract the disas struct to a header file | Alexander Graf | 1 | -23/+1 |
| 2013-09-10 | target-arm: Abstract out load/store from a vaddr in AArch32 | Peter Maydell | 1 | -124/+210 |
| 2013-09-10 | target-arm: Use sextract32() in branch decode | Peter Maydell | 1 | -2/+3 |
| 2013-09-03 | Merge remote-tracking branch 'mjt/trivial-patches' into staging | Anthony Liguori | 1 | -0/+4 |
| 2013-09-02 | tcg: Change tcg_gen_exit_tb argument to uintptr_t | Richard Henderson | 1 | -1/+1 |
| 2013-09-01 | target-arm: Report unimplemented opcodes (LOG_UNIMP) | Stefan Weil | 1 | -0/+4 |
| 2013-08-20 | target-arm: Support coprocessor registers which do I/O | Peter Maydell | 1 | -3/+13 |
| 2013-07-23 | cpu: Move singlestep_enabled field from CPU_COMMON to CPUState | Andreas Färber | 1 | -3/+4 |
| 2013-07-15 | target-arm: explicitly decode SEVL instruction | Mans Rullgard | 1 | -1/+2 |
| 2013-07-15 | target-arm: implement LDA/STL instructions | Mans Rullgard | 1 | -10/+119 |
| 2013-07-15 | target-arm: add feature flag for ARMv8 | Mans Rullgard | 1 | -0/+1 |
| 2013-07-09 | target-arm: Change gen_intermediate_code_internal() argument to ARMCPU | Andreas Färber | 1 | -4/+5 |
| 2013-06-28 | cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks | Andreas Färber | 1 | -2/+4 |
| 2013-06-14 | Merge remote-tracking branch 'pmaydell/target-arm.next' into staging | Anthony Liguori | 1 | -1/+1 |
| 2013-06-03 | Fix rfe instruction | Peter Chubb | 1 | -1/+1 |
| 2013-06-01 | Remove unnecessary break statements | Stefan Weil | 1 | -1/+0 |
| 2013-05-26 | target-arm: Remove gen_{ld,st}* definitions | Peter Maydell | 1 | -46/+0 |
| 2013-05-26 | target-arm: Remove gen_{ld,st}* from thumb2 decoder | Peter Maydell | 1 | -10/+20 |
