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path: root/target-arm/translate-a64.c
AgeCommit message (Expand)AuthorFilesLines
2014-03-17target-arm: A64: Add FRECPX (reciprocal exponent)Alex Bennée1-1/+69
2014-03-17target-arm: A64: List unsupported shift-imm opcodesPeter Maydell1-2/+11
2014-03-17target-arm: A64: Implement FCVTLPeter Maydell1-0/+47
2014-03-17target-arm: A64: Implement FCVTNPeter Maydell1-1/+23
2014-03-17target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructionsPeter Maydell1-19/+169
2014-03-17target-arm: A64: Implement SHLL, SHLL2Peter Maydell1-1/+31
2014-03-17target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALPPeter Maydell1-1/+74
2014-03-17target-arm: A64: Saturating and narrowing shift opsAlex Bennée1-3/+178
2014-03-17target-arm: A64: Add remaining CLS/Z vector opsAlex Bennée1-1/+35
2014-03-17target-arm: A64: Add FSQRT to C3.6.17 (two misc)Alex Bennée1-1/+12
2014-03-17target-arm: A64: Add last AdvSIMD Integer to FP opsAlex Bennée1-9/+123
2014-03-17target-arm: A64: Fix bug in add_sub_ext handling of rnAlex Bennée1-2/+1
2014-03-17target-arm: A64: Implement PMULL instructionPeter Maydell1-2/+39
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber1-2/+2
2014-03-10target-arm: Fix intptr_t vs tcg_target_longRichard Henderson1-1/+1
2014-02-26target-arm: A64: Implement MSR (immediate) instructionsPeter Maydell1-1/+24
2014-02-26target-arm: A64: Implement WFIPeter Maydell1-1/+4
2014-02-26target-arm: Get MMU index information correct for A64 codePeter Maydell1-1/+1
2014-02-26target-arm: Implement AArch64 CurrentEL sysregPeter Maydell1-0/+7
2014-02-20target-arm: A64: Implement unprivileged load/storePeter Maydell1-32/+37
2014-02-20target-arm: A64: Implement narrowing three-reg-diff operationsPeter Maydell1-1/+59
2014-02-20target-arm: A64: Implement the wide 3-reg-different operationsPeter Maydell1-1/+40
2014-02-20target-arm: A64: Add most remaining three-reg-diff widening opsPeter Maydell1-21/+88
2014-02-20target-arm: A64: Add opcode comments to disas_simd_three_reg_diffPeter Maydell1-11/+11
2014-02-20target-arm: A64: Implement store-exclusive for system modePeter Maydell1-6/+62
2014-02-20target-arm: Remove unnecessary code now read/write fns can't failPeter Maydell1-2/+0
2014-02-20target-arm: Split cpreg access checks out from read/write functionsPeter Maydell1-0/+11
2014-02-20target-arm: Log bad system register accesses with LOG_UNIMPPeter Maydell1-1/+6
2014-02-20target-arm: A64: Implement remaining 3-same instructionsPeter Maydell1-4/+48
2014-02-20target-arm: A64: Implement floating point pairwise insnsAlex Bennée1-38/+86
2014-02-20target-arm: A64: Implement SIMD FP compare and set insnsAlex Bennée1-12/+185
2014-02-20target-arm: A64: Implement scalar three different instructionsPeter Maydell1-1/+94
2014-02-20target-arm: A64: Implement SIMD scalar indexed instructionsPeter Maydell1-33/+82
2014-02-20target-arm: A64: Implement long vector x indexed insnsPeter Maydell1-5/+139
2014-02-20target-arm: A64: Implement plain vector SIMD indexed element insnsPeter Maydell1-1/+247
2014-02-08disas: Implement disassembly output for A64Claudio Fontana1-1/+1
2014-02-08target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc groupPeter Maydell1-3/+20
2014-02-08target-arm: A64: Add 2-reg-misc REV* instructionsAlex Bennée1-1/+70
2014-02-08target-arm: A64: Add narrowing 2-reg-misc instructionsPeter Maydell1-2/+83
2014-02-08target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell1-6/+28
2014-02-08target-arm: A64: Implement 2-register misc compares, ABS, NEGPeter Maydell1-2/+134
2014-02-08target-arm: A64: Add skeleton decode for SIMD 2-reg misc groupPeter Maydell1-1/+109
2014-02-08target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg miscPeter Maydell1-1/+86
2014-02-08target-arm: A64: Implement remaining integer scalar-3-same insnsPeter Maydell1-19/+87
2014-02-08target-arm: A64: Implement scalar pairwise opsPeter Maydell1-1/+113
2014-02-08target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMDPeter Maydell1-1/+123
2014-02-08target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insnsPeter Maydell1-4/+127
2014-02-08target-arm: A64: Implement SIMD 3-reg-same shift and saturate insnsPeter Maydell1-22/+112
2014-01-31target-arm: A64: Add SIMD shift by immediateAlex Bennée1-2/+373
2014-01-31target-arm: A64: Add simple SIMD 3-same floating point opsPeter Maydell1-2/+188
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