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path: root/target-arm/translate-a64.c
AgeCommit message (Expand)AuthorFilesLines
2016-09-16target-aarch64: Generate fences for aarch64Pranith Kumar1-1/+26
2016-06-06target-arm: A64: Create Instruction Syndromes for Data AbortsEdgar E. Iglesias1-22/+118
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini1-0/+1
2016-05-12tcg: Allow goto_tb to any target PC in user modeSergey Fedorov1-0/+2
2016-05-12target-arm/translate-a64.c: Unify some of the ldst_reg decodingEdgar E. Iglesias1-18/+23
2016-05-12target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9Edgar E. Iglesias1-2/+2
2016-03-22target-arm: dfilter support for in_asmAlex Bennée1-1/+2
2016-03-04target-arm: introduce tbflag for endiannessPeter Crosthwaite1-1/+1
2016-03-04target-arm: a64: Add endianness supportPeter Crosthwaite1-19/+30
2016-03-04target-arm: introduce disas flag for endiannessPaolo Bonzini1-0/+1
2016-03-04target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini1-3/+3
2016-02-11target-arm: Add isread parameter to CPAccessFnsPeter Maydell1-2/+4
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson1-3/+3
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini1-0/+1
2016-01-18target-arm: Clean up includesPeter Maydell1-5/+1
2015-11-24target-arm/translate-a64.c: Correct unallocated checks for ldst_exclPeter Maydell1-13/+2
2015-11-12target-arm: Update PC before calling gen_helper_check_breakpoints()Sergey Fedorov1-0/+1
2015-11-03target-arm: Report S/NS status in the CPU debug logsPeter Maydell1-1/+10
2015-11-03target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32Peter Maydell1-3/+5
2015-10-28target-*: Advance pc after recognizing a breakpointRichard Henderson1-2/+5
2015-10-16target-arm: Fix CPU breakpoint handlingSergey Fedorov1-5/+12
2015-10-16target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin1-1/+7
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-27/+3
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-0/+3
2015-10-07target-arm: Add condexec state to insn_startRichard Henderson1-1/+1
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson1-13/+13
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-3/+3
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-4/+1
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson1-1/+1
2015-09-14target-arm: Use tcg_gen_extrh_i64_i32Richard Henderson1-25/+9
2015-09-14target-arm: Recognize RORRichard Henderson1-12/+21
2015-09-14target-arm: Eliminate unnecessary zero-extend in disas_bitfieldRichard Henderson1-1/+5
2015-09-14target-arm: Recognize UXTB, UXTH, LSR, LSLRichard Henderson1-0/+17
2015-09-14target-arm: Recognize SXTB, SXTH, SXTW, ASRRichard Henderson1-1/+23
2015-09-14target-arm: Implement fcsel with movcondRichard Henderson1-28/+17
2015-09-14target-arm: Implement ccmp branchlessRichard Henderson1-16/+58
2015-09-14target-arm: Use setcond and movcond for cselRichard Henderson1-36/+49
2015-09-14target-arm: Share all common TCG temporariesRichard Henderson1-22/+0
2015-09-08target-arm: Fix default_exception_el() function for the case when EL3 is not ...Sergey Sorokin1-1/+5
2015-09-07target-arm: Wire up HLT 0xf000 as the A64 semihosting instructionPeter Maydell1-2/+22
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson1-30/+30
2015-07-06target-arm: Split DISAS_YIELD from DISAS_WFEPeter Maydell1-0/+6
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite1-1/+1
2015-05-29target-arm: Don't halt on WFI unless we don't have any workPeter Maydell1-0/+4
2015-05-29target-arm: Extend FP checks to use an ELGreg Bellows1-4/+4
2015-05-29target-arm: Make singlestate TB flags common between AArch32/64Peter Maydell1-2/+2
2015-05-29target-arm: Add exception target el infrastructureGreg Bellows1-12/+22
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-13/+13
2015-02-13Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150212' into stagingPeter Maydell1-7/+3
2015-02-13target-arm: A64: Avoid signed shifts in disas_ldst_pair()Peter Maydell1-1/+1
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