Age | Commit message (Expand) | Author | Files | Lines |
2016-10-17 | target-arm: Comments added to identify cases in a switch | Thomas Hanson | 1 | -3/+3 |
2016-10-17 | target-arm: Code changes to implement overwrite of tag field on PC load | Thomas Hanson | 1 | -5/+77 |
2016-10-17 | target-arm: Infrastucture changes to enable handling of tagged address loadin... | Thomas Hanson | 1 | -0/+2 |
2016-10-04 | target-arm: A64: Fix decoding of iss_sf in disas_ld_lit | Edgar E. Iglesias | 1 | -1/+1 |
2016-09-16 | target-aarch64: Generate fences for aarch64 | Pranith Kumar | 1 | -1/+26 |
2016-06-06 | target-arm: A64: Create Instruction Syndromes for Data Aborts | Edgar E. Iglesias | 1 | -22/+118 |
2016-05-19 | cpu: move exec-all.h inclusion out of cpu.h | Paolo Bonzini | 1 | -0/+1 |
2016-05-12 | tcg: Allow goto_tb to any target PC in user mode | Sergey Fedorov | 1 | -0/+2 |
2016-05-12 | target-arm/translate-a64.c: Unify some of the ldst_reg decoding | Edgar E. Iglesias | 1 | -18/+23 |
2016-05-12 | target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9 | Edgar E. Iglesias | 1 | -2/+2 |
2016-03-22 | target-arm: dfilter support for in_asm | Alex Bennée | 1 | -1/+2 |
2016-03-04 | target-arm: introduce tbflag for endianness | Peter Crosthwaite | 1 | -1/+1 |
2016-03-04 | target-arm: a64: Add endianness support | Peter Crosthwaite | 1 | -19/+30 |
2016-03-04 | target-arm: introduce disas flag for endianness | Paolo Bonzini | 1 | -0/+1 |
2016-03-04 | target-arm: implement SCTLR.B, drop bswap_code | Paolo Bonzini | 1 | -3/+3 |
2016-02-11 | target-arm: Add isread parameter to CPAccessFns | Peter Maydell | 1 | -2/+4 |
2016-02-09 | tcg: Change tcg_global_mem_new_* to take a TCGv_ptr | Richard Henderson | 1 | -3/+3 |
2016-02-03 | log: do not unnecessarily include qom/cpu.h | Paolo Bonzini | 1 | -0/+1 |
2016-01-18 | target-arm: Clean up includes | Peter Maydell | 1 | -5/+1 |
2015-11-24 | target-arm/translate-a64.c: Correct unallocated checks for ldst_excl | Peter Maydell | 1 | -13/+2 |
2015-11-12 | target-arm: Update PC before calling gen_helper_check_breakpoints() | Sergey Fedorov | 1 | -0/+1 |
2015-11-03 | target-arm: Report S/NS status in the CPU debug logs | Peter Maydell | 1 | -1/+10 |
2015-11-03 | target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32 | Peter Maydell | 1 | -3/+5 |
2015-10-28 | target-*: Advance pc after recognizing a breakpoint | Richard Henderson | 1 | -2/+5 |
2015-10-16 | target-arm: Fix CPU breakpoint handling | Sergey Fedorov | 1 | -5/+12 |
2015-10-16 | target-arm: Break the TB after ISB to execute self-modified code correctly | Sergey Sorokin | 1 | -1/+7 |
2015-10-07 | tcg: Remove gen_intermediate_code_pc | Richard Henderson | 1 | -27/+3 |
2015-10-07 | tcg: Add TCG_MAX_INSNS | Richard Henderson | 1 | -0/+3 |
2015-10-07 | target-arm: Add condexec state to insn_start | Richard Henderson | 1 | -1/+1 |
2015-10-07 | target-*: Introduce and use cpu_breakpoint_test | Richard Henderson | 1 | -13/+13 |
2015-10-07 | target-*: Increment num_insns immediately after tcg_gen_insn_start | Richard Henderson | 1 | -3/+3 |
2015-10-07 | target-*: Unconditionally emit tcg_gen_insn_start | Richard Henderson | 1 | -4/+1 |
2015-10-07 | tcg: Rename debug_insn_start to insn_start | Richard Henderson | 1 | -1/+1 |
2015-09-14 | target-arm: Use tcg_gen_extrh_i64_i32 | Richard Henderson | 1 | -25/+9 |
2015-09-14 | target-arm: Recognize ROR | Richard Henderson | 1 | -12/+21 |
2015-09-14 | target-arm: Eliminate unnecessary zero-extend in disas_bitfield | Richard Henderson | 1 | -1/+5 |
2015-09-14 | target-arm: Recognize UXTB, UXTH, LSR, LSL | Richard Henderson | 1 | -0/+17 |
2015-09-14 | target-arm: Recognize SXTB, SXTH, SXTW, ASR | Richard Henderson | 1 | -1/+23 |
2015-09-14 | target-arm: Implement fcsel with movcond | Richard Henderson | 1 | -28/+17 |
2015-09-14 | target-arm: Implement ccmp branchless | Richard Henderson | 1 | -16/+58 |
2015-09-14 | target-arm: Use setcond and movcond for csel | Richard Henderson | 1 | -36/+49 |
2015-09-14 | target-arm: Share all common TCG temporaries | Richard Henderson | 1 | -22/+0 |
2015-09-08 | target-arm: Fix default_exception_el() function for the case when EL3 is not ... | Sergey Sorokin | 1 | -1/+5 |
2015-09-07 | target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction | Peter Maydell | 1 | -2/+22 |
2015-08-24 | tcg: Remove tcg_gen_trunc_i64_i32 | Richard Henderson | 1 | -30/+30 |
2015-07-06 | target-arm: Split DISAS_YIELD from DISAS_WFE | Peter Maydell | 1 | -0/+6 |
2015-06-22 | disas: Remove uses of CPU env | Peter Crosthwaite | 1 | -1/+1 |
2015-05-29 | target-arm: Don't halt on WFI unless we don't have any work | Peter Maydell | 1 | -0/+4 |
2015-05-29 | target-arm: Extend FP checks to use an EL | Greg Bellows | 1 | -4/+4 |
2015-05-29 | target-arm: Make singlestate TB flags common between AArch32/64 | Peter Maydell | 1 | -2/+2 |