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path: root/target-arm/translate-a64.c
AgeCommit message (Expand)AuthorFilesLines
2014-02-08target-arm: A64: Add narrowing 2-reg-misc instructionsPeter Maydell1-2/+83
2014-02-08target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell1-6/+28
2014-02-08target-arm: A64: Implement 2-register misc compares, ABS, NEGPeter Maydell1-2/+134
2014-02-08target-arm: A64: Add skeleton decode for SIMD 2-reg misc groupPeter Maydell1-1/+109
2014-02-08target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg miscPeter Maydell1-1/+86
2014-02-08target-arm: A64: Implement remaining integer scalar-3-same insnsPeter Maydell1-19/+87
2014-02-08target-arm: A64: Implement scalar pairwise opsPeter Maydell1-1/+113
2014-02-08target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMDPeter Maydell1-1/+123
2014-02-08target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insnsPeter Maydell1-4/+127
2014-02-08target-arm: A64: Implement SIMD 3-reg-same shift and saturate insnsPeter Maydell1-22/+112
2014-01-31target-arm: A64: Add SIMD shift by immediateAlex Bennée1-2/+373
2014-01-31target-arm: A64: Add simple SIMD 3-same floating point opsPeter Maydell1-2/+188
2014-01-31target-arm: A64: Add integer ops from SIMD 3-same groupPeter Maydell1-1/+164
2014-01-31target-arm: A64: Add logic ops from SIMD 3 same groupPeter Maydell1-1/+72
2014-01-31target-arm: A64: Add top level decode for SIMD 3-same groupPeter Maydell1-1/+44
2014-01-31target-arm: A64: Add SIMD scalar 3 same add, sub and compare opsPeter Maydell1-1/+130
2014-01-31target-arm: A64: Add SIMD three-different ABDL instructionsPeter Maydell1-2/+33
2014-01-31target-arm: A64: Add SIMD three-different multiply accumulate insnsPeter Maydell1-1/+232
2014-01-31target-arm: Move arm_rmode_to_sf to a shared location.Will Newton1-28/+0
2014-01-31target-arm: A64: Add SIMD scalar copy instructionsPeter Maydell1-1/+42
2014-01-31target-arm: A64: Add SIMD modified immediate groupAlex Bennée1-1/+119
2014-01-31target-arm: A64: Add SIMD copy operationsAlex Bennée1-1/+209
2014-01-31target-arm: A64: Add SIMD across-lanes instructionsMichael Matz1-1/+176
2014-01-31target-arm: A64: Add SIMD ZIP/UZP/TRNMichael Matz1-1/+75
2014-01-31target-arm: A64: Add SIMD TBL/TBLXMichael Matz1-1/+54
2014-01-31target-arm: A64: Add SIMD EXTPeter Maydell1-1/+78
2014-01-31target-arm: A64: Add decode skeleton for SIMD data processing insnsAlex Bennée1-1/+305
2014-01-31target-arm: A64: Add SIMD ld/st singlePeter Maydell1-2/+142
2014-01-31target-arm: A64: Add SIMD ld/st multipleAlex Bennée1-2/+248
2014-01-08target-arm: A64: Add support for FCVT between half, single and doublePeter Maydell1-1/+74
2014-01-08target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructionsPeter Maydell1-1/+141
2014-01-08target-arm: A64: Add floating-point<->integer conversion instructionsWill Newton1-3/+20
2014-01-08target-arm: A64: Add floating-point<->fixed-point instructionsAlexander Graf1-1/+185
2014-01-08target-arm: A64: Add support for floating point cond selectClaudio Fontana1-1/+44
2014-01-08target-arm: A64: Add support for floating point conditional compareClaudio Fontana1-1/+34
2014-01-08target-arm: A64: Add support for floating point compareClaudio Fontana1-1/+64
2014-01-08target-arm: A64: Add fmov (scalar, immediate) instructionAlexander Graf1-1/+31
2014-01-08target-arm: A64: Add "Floating-point data-processing (3 source)" insnsAlexander Graf1-1/+94
2014-01-08target-arm: A64: Add "Floating-point data-processing (2 source)" insnsAlexander Graf1-1/+181
2014-01-08target-arm: A64: Fix vector register access on bigendian hostsPeter Maydell1-34/+35
2014-01-08target-arm: A64: Add support for dumping AArch64 VFP register stateAlexander Graf1-0/+16
2014-01-08target-arm: A64: support for ld/st/cl exclusiveMichael Matz1-3/+153
2014-01-08target-arm: aarch64: add support for ld litAlexander Graf1-2/+45
2014-01-08target-arm: A64: add support for conditional compare insnsClaudio Fontana1-13/+60
2014-01-08target-arm: A64: add support for add/sub with carryClaudio Fontana1-2/+103
2014-01-07target-arm: A64: Implement minimal set of EL0-visible sysregsPeter Maydell1-0/+52
2014-01-07target-arm: A64: Implement MRS/MSR/SYS/SYSLPeter Maydell1-30/+82
2014-01-07target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoderPeter Maydell1-0/+2
2013-12-23target-arm: A64: implement FMOVPeter Maydell1-1/+85
2013-12-23target-arm: A64: Add decoder skeleton for FP instructionsPeter Maydell1-1/+169
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