| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2015-09-15 | target-arm: Use new revbit functions | Richard Henderson | 1 | -11/+1 |
| 2015-09-14 | target-arm: Add VMPIDR_EL2 | Edgar E. Iglesias | 1 | -2/+24 |
| 2015-09-14 | target-arm: Break out mpidr_read_val() | Edgar E. Iglesias | 1 | -1/+6 |
| 2015-09-14 | target-arm: Add VPIDR_EL2 | Edgar E. Iglesias | 1 | -1/+41 |
| 2015-09-14 | target-arm: Suppress EPD for S2, EL2 and EL3 translations | Edgar E. Iglesias | 1 | -2/+4 |
| 2015-09-14 | target-arm: Suppress TBI for S2 translations | Edgar E. Iglesias | 1 | -1/+3 |
| 2015-09-14 | target-arm: Add VTTBR_EL2 | Edgar E. Iglesias | 1 | -2/+32 |
| 2015-09-14 | target-arm: Add VTCR_EL2 | Edgar E. Iglesias | 1 | -2/+41 |
| 2015-09-11 | tlb: Add "ifetch" argument to cpu_mmu_index() | Benjamin Herrenschmidt | 1 | -2/+2 |
| 2015-09-11 | maint: remove / fix many doubled words | Daniel P. Berrange | 1 | -1/+1 |
| 2015-09-08 | target-arm: Add AArch64 access to PAR_EL1 | Edgar E. Iglesias | 1 | -0/+6 |
| 2015-09-08 | target-arm: Correct opc1 for AT_S12Exx | Edgar E. Iglesias | 1 | -4/+4 |
| 2015-09-07 | target-arm: Fix AArch32:AArch64 general-purpose register mapping | Sergey Sorokin | 1 | -32/+32 |
| 2015-09-07 | arm: Remove hw_error() usages. | Peter Crosthwaite | 1 | -1/+1 |
| 2015-09-07 | target-arm: Improve semihosting debug prints | Christopher Covington | 1 | -3/+9 |
| 2015-08-25 | target-arm: Implement AArch64 TLBI operations on IPAs | Peter Maydell | 1 | -0/+55 |
| 2015-08-25 | target-arm: Implement missing EL3 TLB invalidate operations | Peter Maydell | 1 | -0/+76 |
| 2015-08-25 | target-arm: Implement missing EL2 TLBI operations | Peter Maydell | 1 | -0/+22 |
| 2015-08-25 | target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch | Peter Maydell | 1 | -43/+129 |
| 2015-08-25 | target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order | Peter Maydell | 1 | -8/+8 |
| 2015-08-25 | target-arm: Implement AArch32 ATS1H* operations | Peter Maydell | 1 | -0/+22 |
| 2015-08-25 | target-arm: Enable the AArch32 ATS12NSO ops | Peter Maydell | 1 | -5/+11 |
| 2015-08-25 | target-arm: Wire up AArch64 EL2 and EL3 address translation ops | Peter Maydell | 1 | -2/+41 |
| 2015-08-25 | target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations | Peter Maydell | 1 | -0/+5 |
| 2015-08-25 | target-arm: Implement missing ACTLR registers | Peter Maydell | 1 | -6/+15 |
| 2015-08-25 | target-arm: Implement missing AFSR registers | Peter Maydell | 1 | -0/+24 |
| 2015-08-25 | target-arm: Implement missing AMAIR registers | Peter Maydell | 1 | -0/+21 |
| 2015-08-25 | target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers | Peter Maydell | 1 | -0/+8 |
| 2015-08-13 | target-arm: Add AArch32 banked register access to secure physical timer | Peter Maydell | 1 | -0/+27 |
| 2015-08-13 | target-arm: Add the AArch64 view of the Secure physical timer | Peter Maydell | 1 | -0/+87 |
| 2015-08-13 | target-arm: Add debug check for mismatched cpreg resets | Peter Maydell | 1 | -1/+1 |
| 2015-08-13 | target-arm: Add the Hypervisor timer | Edgar E. Iglesias | 1 | -0/+68 |
| 2015-08-13 | target-arm: Pass timeridx as argument to various timer functions | Edgar E. Iglesias | 1 | -22/+77 |
| 2015-08-13 | target-arm: Rename and move gt_cnt_reset | Edgar E. Iglesias | 1 | -7/+5 |
| 2015-08-13 | target-arm: Add CNTHCTL_EL2 | Edgar E. Iglesias | 1 | -2/+31 |
| 2015-08-13 | target-arm: Add CNTVOFF_EL2 | Edgar E. Iglesias | 1 | -6/+41 |
| 2015-07-15 | target-arm: Fix broken SCTLR_EL3 reset | Peter Maydell | 1 | -0/+1 |
| 2015-07-06 | target-arm: fix write helper for TLBI ALLE1IS | Sergey Fedorov | 1 | -1/+1 |
| 2015-06-19 | semihosting: create SemihostingConfig structure and semihost.h | Leon Alrae | 1 | -3/+4 |
| 2015-06-19 | target-arm: Implement PMSAv7 MPU | Peter Crosthwaite | 1 | -1/+173 |
| 2015-06-19 | target-arm: Add registers for PMSAv7 | Peter Crosthwaite | 1 | -7/+83 |
| 2015-06-19 | target-arm/helper.c: define MPUIR register | Peter Crosthwaite | 1 | -0/+10 |
| 2015-06-19 | target-arm: Do not reset sysregs marked as ALIAS | Sergey Fedorov | 1 | -19/+9 |
| 2015-06-15 | arm: helper: rename get_phys_addr_mpu | Peter Crosthwaite | 1 | -5/+5 |
| 2015-06-15 | arm: Implement uniprocessor with MP config | Peter Crosthwaite | 1 | -2/+4 |
| 2015-06-15 | arm: Refactor get_phys_addr FSR return mechanism | Peter Crosthwaite | 1 | -58/+70 |
| 2015-06-15 | arm: helper: Factor out CP regs common to [pv]msa | Peter Crosthwaite | 1 | -9/+14 |
| 2015-06-15 | arm: Don't add v7mp registers in MPU systems | Peter Crosthwaite | 1 | -1/+2 |
| 2015-06-15 | arm: Do not define TLBTR in PMSA systems | Peter Crosthwaite | 1 | -3/+10 |
| 2015-06-15 | target-arm: Use the kernel's idea of MPIDR if we're using KVM | Pavel Fedin | 1 | -6/+3 |
