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path: root/target-arm/helper.c
AgeCommit message (Expand)AuthorFilesLines
2015-08-25target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registersPeter Maydell1-0/+8
2015-08-13target-arm: Add AArch32 banked register access to secure physical timerPeter Maydell1-0/+27
2015-08-13target-arm: Add the AArch64 view of the Secure physical timerPeter Maydell1-0/+87
2015-08-13target-arm: Add debug check for mismatched cpreg resetsPeter Maydell1-1/+1
2015-08-13target-arm: Add the Hypervisor timerEdgar E. Iglesias1-0/+68
2015-08-13target-arm: Pass timeridx as argument to various timer functionsEdgar E. Iglesias1-22/+77
2015-08-13target-arm: Rename and move gt_cnt_resetEdgar E. Iglesias1-7/+5
2015-08-13target-arm: Add CNTHCTL_EL2Edgar E. Iglesias1-2/+31
2015-08-13target-arm: Add CNTVOFF_EL2Edgar E. Iglesias1-6/+41
2015-07-15target-arm: Fix broken SCTLR_EL3 resetPeter Maydell1-0/+1
2015-07-06target-arm: fix write helper for TLBI ALLE1ISSergey Fedorov1-1/+1
2015-06-19semihosting: create SemihostingConfig structure and semihost.hLeon Alrae1-3/+4
2015-06-19target-arm: Implement PMSAv7 MPUPeter Crosthwaite1-1/+173
2015-06-19target-arm: Add registers for PMSAv7Peter Crosthwaite1-7/+83
2015-06-19target-arm/helper.c: define MPUIR registerPeter Crosthwaite1-0/+10
2015-06-19target-arm: Do not reset sysregs marked as ALIASSergey Fedorov1-19/+9
2015-06-15arm: helper: rename get_phys_addr_mpuPeter Crosthwaite1-5/+5
2015-06-15arm: Implement uniprocessor with MP configPeter Crosthwaite1-2/+4
2015-06-15arm: Refactor get_phys_addr FSR return mechanismPeter Crosthwaite1-58/+70
2015-06-15arm: helper: Factor out CP regs common to [pv]msaPeter Crosthwaite1-9/+14
2015-06-15arm: Don't add v7mp registers in MPU systemsPeter Crosthwaite1-1/+2
2015-06-15arm: Do not define TLBTR in PMSA systemsPeter Crosthwaite1-3/+10
2015-06-15target-arm: Use the kernel's idea of MPIDR if we're using KVMPavel Fedin1-6/+3
2015-06-15target-arm: add AArch32 MIDR aliases in ARMv8Sergey Fedorov1-3/+7
2015-06-15target-arm: Fix REVIDR reset valueSergey Fedorov1-3/+2
2015-06-15target-arm: use extended address bits from supersection short descriptorSergey Fedorov1-0/+2
2015-06-15target-arm: Handle "extended small page" descriptors correctlyPeter Maydell1-4/+9
2015-06-02target-arm: Remove v8_ prefix from names of non-v8-specific cpreg arraysPeter Maydell1-4/+4
2015-06-02Revert "target-arm: Avoid g_hash_table_get_keys()"Markus Armbruster1-10/+2
2015-06-02target-arm: Add TLBI_VAE2{IS}Edgar E. Iglesias1-0/+8
2015-06-02target-arm: Add TLBI_ALLE2Edgar E. Iglesias1-0/+4
2015-06-02target-arm: Add TLBI_ALLE1{IS}Edgar E. Iglesias1-0/+8
2015-06-02target-arm: Add TTBR0_EL2Edgar E. Iglesias1-0/+14
2015-06-02target-arm: Add TPIDR_EL2Edgar E. Iglesias1-0/+7
2015-06-02target-arm: Add SCTLR_EL2Edgar E. Iglesias1-0/+7
2015-06-02target-arm: Add TCR_EL2Edgar E. Iglesias1-0/+8
2015-06-02target-arm: Add MAIR_EL2Edgar E. Iglesias1-0/+15
2015-06-02target-arm: Break down TLB_LOCKDOWNEdgar E. Iglesias1-12/+18
2015-05-29target-arm: Add AArch64 CPTR registersGreg Bellows1-1/+39
2015-05-29target-arm: Update interrupt handling to use target ELGreg Bellows1-37/+4
2015-05-29target-arm: Move setting of exception info into tlb_fillPeter Maydell1-40/+7
2015-05-18target-arm: Remove unneeded '+'Edgar E. Iglesias1-1/+1
2015-05-18target-arm: Correct accessfn for CNTV_TVAL_EL0Edgar E. Iglesias1-0/+1
2015-05-18target-arm: Correct accessfn for CNTP_{CT}VAL_EL0Edgar E. Iglesias1-1/+2
2015-05-18target-arm: Add EL3 and EL2 TCR checkingGreg Bellows1-13/+32
2015-05-18target-arm: Add TTBR regime function and useGreg Bellows1-5/+19
2015-05-14tcg: Push merged memop+mmu_idx parameter to softmmu routinesRichard Henderson1-4/+6
2015-04-26Allow ARMv8 SCR.SMD updatesGreg Bellows1-1/+3
2015-04-26target-arm: rename c1_coproc to cpacr_el1Sergey Fedorov1-2/+2
2015-04-26target-arm: Add user-mode transaction attributePeter Maydell1-0/+1
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