index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-arm
/
helper.c
Age
Commit message (
Expand
)
Author
Files
Lines
2014-09-29
target-arm: Add support for VIRQ and VFIQ
Edgar E. Iglesias
1
-0
/
+4
2014-09-29
target-arm: Add IRQ and FIQ routing to EL2 and 3
Edgar E. Iglesias
1
-0
/
+17
2014-09-29
target-arm: A64: Emulate the SMC insn
Edgar E. Iglesias
1
-0
/
+3
2014-09-29
target-arm: Add a Hypervisor Trap exception type
Edgar E. Iglesias
1
-0
/
+1
2014-09-29
target-arm: A64: Emulate the HVC insn
Edgar E. Iglesias
1
-1
/
+19
2014-09-29
target-arm: A64: Refactor aarch64_cpu_do_interrupt
Edgar E. Iglesias
1
-0
/
+13
2014-09-29
target-arm: Add SCR_EL3
Edgar E. Iglesias
1
-2
/
+33
2014-09-29
target-arm: Add HCR_EL2
Edgar E. Iglesias
1
-0
/
+34
2014-09-29
target-arm: Don't handle c15_cpar changes via tb_flush()
Peter Maydell
1
-6
/
+1
2014-09-29
target-arm: Implement setting guest breakpoints
Peter Maydell
1
-2
/
+124
2014-09-12
target-arm: Make *IS TLB maintenance ops affect all CPUs
Peter Maydell
1
-12
/
+89
2014-09-12
target-arm: Push legacy wildcard TLB ops back into v6
Peter Maydell
1
-47
/
+55
2014-09-12
target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0
Peter Maydell
1
-0
/
+19
2014-09-12
target-arm: Remove comment about MDSCR_EL1 being dummy implementation
Peter Maydell
1
-3
/
+1
2014-09-12
target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32
Peter Maydell
1
-0
/
+26
2014-09-12
target-arm: Implement handling of fired watchpoints
Peter Maydell
1
-1
/
+6
2014-09-12
target-arm: Move extended_addresses_enabled() to internals.h
Peter Maydell
1
-11
/
+0
2014-09-12
target-arm: Implement setting of watchpoints
Peter Maydell
1
-3
/
+132
2014-08-29
target-arm: Implement pmccfiltr_write function
Alistair Francis
1
-0
/
+9
2014-08-29
target-arm: Remove old code and replace with new functions
Alistair Francis
1
-23
/
+4
2014-08-29
target-arm: Implement pmccntr_sync function
Alistair Francis
1
-0
/
+23
2014-08-29
target-arm: Add arm_ccnt_enabled function
Alistair Francis
1
-0
/
+12
2014-08-29
target-arm: Implement PMCCNTR_EL0 and related registers
Alistair Francis
1
-6
/
+39
2014-08-29
arm: Implement PMCCNTR 32b read-modify-write
Peter Crosthwaite
1
-1
/
+10
2014-08-29
target-arm: Make the ARM PMCCNTR register 64-bit
Alistair Francis
1
-10
/
+9
2014-08-19
target-arm: Implement MDSCR_EL1 as having state
Peter Maydell
1
-1
/
+3
2014-08-19
target-arm: Correctly handle PSTATE.SS when taking exception to AArch32
Peter Maydell
1
-0
/
+4
2014-08-19
target-arm: Adjust debug ID registers per-CPU
Peter Maydell
1
-7
/
+26
2014-08-19
target-arm: Provide both 32 and 64 bit versions of debug registers
Peter Maydell
1
-14
/
+20
2014-08-19
target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14
Peter Maydell
1
-3
/
+8
2014-08-19
target-arm: Collect up the debug cp register definitions
Peter Maydell
1
-32
/
+53
2014-08-04
target-arm: A64: fix TLB flush instructions
Alex Bennée
1
-2
/
+8
2014-08-04
target-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault
Alex Bennée
1
-2
/
+2
2014-08-04
target-arm: Fix bit test in sp_el0_access
Stefan Weil
1
-1
/
+1
2014-08-04
target-arm: Add FAR_EL2 and 3
Edgar E. Iglesias
1
-0
/
+6
2014-08-04
target-arm: Add ESR_EL2 and 3
Edgar E. Iglesias
1
-0
/
+8
2014-08-04
target-arm: Make far_el1 an array
Edgar E. Iglesias
1
-6
/
+6
2014-06-24
Fix new typos (found by codespell)
Stefan Weil
1
-1
/
+1
2014-06-19
target-arm: Add ULL suffix to calculation of page size
Peter Maydell
1
-1
/
+1
2014-06-19
target-arm: implement PD0/PD1 bits for TTBCR
Fabian Aggeler
1
-18
/
+44
2014-06-09
target-arm: Fix errors in writes to generic timer control registers
Peter Maydell
1
-3
/
+3
2014-06-09
target-arm: A32/T32: Mask CRC value in calling code, not helper
Peter Maydell
1
-19
/
+6
2014-06-09
target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables
Ian Campbell
1
-9
/
+8
2014-06-09
target-arm: Prepare cpreg writefns/readfns for EL3/SecExt
Fabian Aggeler
1
-14
/
+14
2014-06-05
softmmu: introduce cpu_ldst.h
Paolo Bonzini
1
-2
/
+1
2014-06-05
target-arm: move arm_*_code to a separate file
Paolo Bonzini
1
-0
/
+1
2014-05-28
tcg: Invert the inclusion of helper.h
Richard Henderson
1
-1
/
+1
2014-05-27
target-arm: A64: Register VBAR_EL3
Edgar E. Iglesias
1
-0
/
+5
2014-05-27
target-arm: A64: Register VBAR_EL2
Edgar E. Iglesias
1
-0
/
+21
2014-05-27
target-arm: Make vbar_write writeback to any CPREG
Edgar E. Iglesias
1
-1
/
+1
[next]