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path: root/target-arm/helper.c
AgeCommit message (Expand)AuthorFilesLines
2015-10-16target-arm: Add MDCR_EL2Sergey Fedorov1-0/+12
2015-10-16target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregsDavorin Mista1-2/+23
2015-10-16target-arm: Avoid calling arm_el_is_aa64() function for unimplemented ELSergey Sorokin1-2/+13
2015-10-16target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin1-1/+5
2015-10-16target-arm: Add missing 'static' attributeStefan Weil1-1/+1
2015-09-25arm: clarify the use of muldiv64()Laurent Vivier1-6/+8
2015-09-15target-arm: Use new revbit functionsRichard Henderson1-11/+1
2015-09-14target-arm: Add VMPIDR_EL2Edgar E. Iglesias1-2/+24
2015-09-14target-arm: Break out mpidr_read_val()Edgar E. Iglesias1-1/+6
2015-09-14target-arm: Add VPIDR_EL2Edgar E. Iglesias1-1/+41
2015-09-14target-arm: Suppress EPD for S2, EL2 and EL3 translationsEdgar E. Iglesias1-2/+4
2015-09-14target-arm: Suppress TBI for S2 translationsEdgar E. Iglesias1-1/+3
2015-09-14target-arm: Add VTTBR_EL2Edgar E. Iglesias1-2/+32
2015-09-14target-arm: Add VTCR_EL2Edgar E. Iglesias1-2/+41
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt1-2/+2
2015-09-11maint: remove / fix many doubled wordsDaniel P. Berrange1-1/+1
2015-09-08target-arm: Add AArch64 access to PAR_EL1Edgar E. Iglesias1-0/+6
2015-09-08target-arm: Correct opc1 for AT_S12ExxEdgar E. Iglesias1-4/+4
2015-09-07target-arm: Fix AArch32:AArch64 general-purpose register mappingSergey Sorokin1-32/+32
2015-09-07arm: Remove hw_error() usages.Peter Crosthwaite1-1/+1
2015-09-07target-arm: Improve semihosting debug printsChristopher Covington1-3/+9
2015-08-25target-arm: Implement AArch64 TLBI operations on IPAsPeter Maydell1-0/+55
2015-08-25target-arm: Implement missing EL3 TLB invalidate operationsPeter Maydell1-0/+76
2015-08-25target-arm: Implement missing EL2 TLBI operationsPeter Maydell1-0/+22
2015-08-25target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touchPeter Maydell1-43/+129
2015-08-25target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric orderPeter Maydell1-8/+8
2015-08-25target-arm: Implement AArch32 ATS1H* operationsPeter Maydell1-0/+22
2015-08-25target-arm: Enable the AArch32 ATS12NSO opsPeter Maydell1-5/+11
2015-08-25target-arm: Wire up AArch64 EL2 and EL3 address translation opsPeter Maydell1-2/+41
2015-08-25target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translationsPeter Maydell1-0/+5
2015-08-25target-arm: Implement missing ACTLR registersPeter Maydell1-6/+15
2015-08-25target-arm: Implement missing AFSR registersPeter Maydell1-0/+24
2015-08-25target-arm: Implement missing AMAIR registersPeter Maydell1-0/+21
2015-08-25target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registersPeter Maydell1-0/+8
2015-08-13target-arm: Add AArch32 banked register access to secure physical timerPeter Maydell1-0/+27
2015-08-13target-arm: Add the AArch64 view of the Secure physical timerPeter Maydell1-0/+87
2015-08-13target-arm: Add debug check for mismatched cpreg resetsPeter Maydell1-1/+1
2015-08-13target-arm: Add the Hypervisor timerEdgar E. Iglesias1-0/+68
2015-08-13target-arm: Pass timeridx as argument to various timer functionsEdgar E. Iglesias1-22/+77
2015-08-13target-arm: Rename and move gt_cnt_resetEdgar E. Iglesias1-7/+5
2015-08-13target-arm: Add CNTHCTL_EL2Edgar E. Iglesias1-2/+31
2015-08-13target-arm: Add CNTVOFF_EL2Edgar E. Iglesias1-6/+41
2015-07-15target-arm: Fix broken SCTLR_EL3 resetPeter Maydell1-0/+1
2015-07-06target-arm: fix write helper for TLBI ALLE1ISSergey Fedorov1-1/+1
2015-06-19semihosting: create SemihostingConfig structure and semihost.hLeon Alrae1-3/+4
2015-06-19target-arm: Implement PMSAv7 MPUPeter Crosthwaite1-1/+173
2015-06-19target-arm: Add registers for PMSAv7Peter Crosthwaite1-7/+83
2015-06-19target-arm/helper.c: define MPUIR registerPeter Crosthwaite1-0/+10
2015-06-19target-arm: Do not reset sysregs marked as ALIASSergey Fedorov1-19/+9
2015-06-15arm: helper: rename get_phys_addr_mpuPeter Crosthwaite1-5/+5
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