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path: root/target-arm/cpu64.c
AgeCommit message (Expand)AuthorFilesLines
2014-10-24target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"Peter Maydell1-1/+1
2014-10-24target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring1-0/+2
2014-09-25target-arm: Use cpu_exec_interrupt qom hookRichard Henderson1-0/+1
2014-08-29target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register valuesPeter Maydell1-1/+2
2014-08-19target-arm: Adjust debug ID registers per-CPUPeter Maydell1-0/+1
2014-06-09target-arm: VFPv4 implies half-precision extensionPeter Maydell1-2/+0
2014-06-09target-arm: Clean up handling of ARMv8 optional feature bitsPeter Maydell1-0/+10
2014-06-09target-arm: Remove unnecessary setting of feature bitsPeter Maydell1-2/+0
2014-06-09target-arm/cpu64.c: Actually register Cortex-A57 impdef registersPeter Maydell1-0/+1
2014-04-17target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32Peter Maydell1-1/+0
2014-04-17target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pcPeter Maydell1-4/+8
2014-04-17target-arm: Implement CBAR for Cortex-A57Peter Maydell1-0/+1
2014-04-17target-arm: Implement Cortex-A57 implementation-defined system registersPeter Maydell1-0/+55
2014-04-17target-arm: Remove THUMB2EE feature from AArch64 'any' CPUPeter Maydell1-1/+0
2014-04-17target-arm: Add Cortex-A57 processorPeter Maydell1-0/+43
2014-04-17target-arm: Implement AArch64 EL1 exception handlingRob Herring1-0/+1
2014-04-17target-arm: A64: Implement DC ZVAPeter Maydell1-0/+1
2014-02-26target-arm: A64: Make cache ID registers visible to AArch64Peter Maydell1-0/+1
2014-01-14target-arm: Switch ARMCPUInfo arrays to use terminator entriesPeter Maydell1-9/+6
2014-01-08target-arm: fix build with gcc 4.8.2Michael S. Tsirkin1-0/+6
2013-12-17target-arm: A64: add set_pc cpu methodAlexander Graf1-0/+11
2013-09-10target-arm: Add AArch64 gdbstub supportAlexander Graf1-0/+4
2013-09-10target-arm: Add AArch64 translation stubAlexander Graf1-0/+3
2013-09-10target-arm: Add new AArch64CPUInfo base class and subclassesPeter Maydell1-0/+111
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