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2015-06-15target-arm/cpu.h: remove pending_exceptionAlex Bennée1-1/+0
This isn't used by any of the code. In fact it looks like it was never used as it came in with ARMv7 support. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1434020015-8868-1-git-send-email-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29target-arm: Move TB flags down to fill gapPeter Maydell1-2/+2
Deleting the now-unused ARM_TBFLAG_CPACR_FPEN left a gap in the bit usage; move the following ARM_TBFLAG_XSCALE_CPAR and ARM_TBFLAG_NS_SHIFT down 3 bits to fill the gap. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Extend FP checks to use an ELGreg Bellows1-22/+70
Extend the ARM disassemble context to take a target exception EL instead of a boolean enable. This change reverses the polarity of the check making a value of 0 indicate floating point enabled (no exception). Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: Use a common TB flag field for AArch32 and AArch64; CPTR_EL2 exists in v7; CPTR_EL2 should trap for EL2 accesses; CPTR_EL2 should not trap for secure accesses; CPTR_EL3 should trap for EL3 accesses; CPACR traps for secure accesses should trap to EL3 if EL3 is AArch32] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Make singlestate TB flags common between AArch32/64Peter Maydell1-42/+27
Currently we keep the TB flags PSTATE_SS and SS_ACTIVE in different bit positions for AArch64 and AArch32. Replace these separate definitions with a single common flag in the upper part of the flags word. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Add AArch64 CPTR registersGreg Bellows1-0/+5
Adds CPTR_EL2/3 system registers definitions and access function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: merge CPTR_EL2 and HCPTR definitions into a single def using STATE_BOTH; don't use readfn/writefn to implement RAZ/WI registers; don't use accessfn for the no-EL2 CPTR_EL2; fix cpacr_access logic to catch EL2 accesses to CPACR being trapped to EL3; use new CP_ACCESS_TRAP_EL[23] rather than setting exception.target_el directly] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Allow cp access functions to indicate traps to EL2 or EL3Peter Maydell1-1/+5
Some coprocessor access functions will need to indicate that the instruction should trap to EL2 or EL3 rather than the default target exception level; add corresponding CPAccessResult enum entries and handling code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Update interrupt handling to use target ELGreg Bellows1-3/+4
Updated the interrupt handling to utilize and report through the target EL exception field. This includes consolidating and cleaning up code where needed. Target EL is now calculated once in arm_cpu_exec_interrupt() and do_interrupt was updated to use the target_el exception field. The necessary code from arm_excp_target_el() was merged in where needed and the function removed. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-4-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29target-arm: Move setting of exception info into tlb_fillPeter Maydell1-2/+0
Move the code which sets exception information out of arm_cpu_handle_mmu_fault and into tlb_fill. tlb_fill is the only caller which wants to raise_exception() so it makes more sense for it to handle the whole of the exception setup. As part of this cleanup, move the user-mode-only implementation function for the handle_mmu_fault CPU method into cpu.c so we don't need to make it globally visible, and rename the softmmu-only utility function arm_cpu_handle_mmu_fault to arm_tlb_fill so it's clear that it's not the same thing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Add exception target el infrastructureGreg Bellows1-0/+1
Add a CPU state exception target EL field that will be used for communicating the EL to which an exception should be routed. Add a disassembly context field for tracking the EL3 architecture needed for determining the target exception EL. Add a target EL argument to the generic exception helper for callers to specify the EL to which the exception should be routed. Extended the helper to set the newly added CPU state exception target el. Added a function for setting the target exception EL and updated calls to helpers to call it. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-2-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-30tcg: Delete unused cpu_pc_from_tb()Peter Crosthwaite1-9/+0
No code uses the cpu_pc_from_tb() function. Delete from tricore and arm which each provide an unused implementation. Update the comment in tcg.h to reflect that this is obsoleted by synchronize_from_tb. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-04-30arm: cpu.h: Remove unused typdefsPeter Crosthwaite1-5/+0
These CP accessor function prototypes are unused. Remove them. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-04-26target-arm: rename c1_coproc to cpacr_el1Sergey Fedorov1-2/+2
Rename the field holding CPACR_EL1 system register state in AArch64 naming style. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> [PMM: also fixed a couple of missed occurrences in cpu.c] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-10cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost1-8/+1
Instead of making cpu_init() return CPUArchState, return CPUState. Changes were made using the Coccinelle semantic patch below. @@ typedef CPUState; identifier e; expression args; type CPUArchState; @@ - e = + cpu = cpu_init(args); - if (!e) { + if (!cpu) { ... } - cpu = ENV_GET_CPU(env); + e = cpu->env_ptr; @@ identifier new_env, new_cpu, env, cpu; type CPUArchState; expression args; @@ -{ - CPUState *cpu = ENV_GET_CPU(env); - CPUArchState *new_env = cpu_init(args); - CPUState *new_cpu = ENV_GET_CPU(new_env); +{ + CPUState *cpu = ENV_GET_CPU(env); + CPUState *new_cpu = cpu_init(args); + CPUArchState *new_env = new_cpu->env_ptr; ... } @@ identifier c, cpu_init_func, cpu_model; type StateType, CPUType; @@ -static inline StateType* cpu_init(const char *cpu_model) -{ - CPUType *c = cpu_init_func(cpu_model); ( - if (c == NULL) { - return NULL; - } - return &c->env; | - if (c) { - return &c->env; - } - return NULL; ) -} +#define cpu_init(cpu_model) CPU(cpu_init_func(cpu_model)) @@ identifier cpu_init_func; identifier model; @@ -#define cpu_init(model) (&cpu_init_func(model)->env) +#define cpu_init(model) CPU(cpu_init_func(model)) Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Max Filippov <jcmvbkbc@gmail.com> [AF: Fixed up cpu_copy() manually] Signed-off-by: Andreas Färber <afaerber@suse.de>
2015-02-13target-arm: Add 32/64-bit register syncGreg Bellows1-0/+2
Add AArch32 to AArch64 register sychronization functions. Replace manual register synchronization with new functions in aarch64_cpu_do_interrupt() and HELPER(exception_return)(). Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1423736974-14254-4-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-02-05target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64Pranavkumar Sawargaonkar1-0/+2
This patch implements a fucntion pointer "virtio_is_big_endian" from "CPUClass" structure for arm/arm64. Function arm_cpu_is_big_endian() is added to determine and return the guest cpu endianness to virtio. This is required for running cross endian guests with virtio on ARM/ARM64. Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> Message-id: 1423130382-18640-3-git-send-email-pranavkumar@linaro.org [PMM: check CPSR_E in env->cpsr_uncached, not env->pstate.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-02-05target-arm: Don't define any MMU_MODE*_SUFFIXesPeter Maydell1-2/+0
target-arm doesn't use any of the MMU-mode specific cpu ldst accessor functions. Suppress their generation by not defining any of the MMU_MODE*_SUFFIX macros. ("user" and "kernel" are too simplistic as descriptions of indexes 0 and 1 anyway.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-02-05target-arm: Define correct mmu_idx values and pass them in TB flagsPeter Maydell1-23/+92
We currently claim that for ARM the mmu_idx should simply be the current exception level. However this isn't actually correct -- secure EL0 and EL1 should have separate indexes from non-secure EL0 and EL1 since their VA->PA mappings may differ. We also will want an index for stage 2 translations when we properly support EL2. Define and document all seven mmu index values that we require, and pass the mmu index in the TB flags rather than exception level or priv/user bit. This change doesn't update the get_phys_addr() code, so our page table walking still assumes a simplistic "user or priv?" model for the moment. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> --- This leaves some odd gaps in the TB flags usage. I will circle back and clean this up later (including moving the other common flags like the singlestep ones to the top of the flags word), but I didn't want to bloat this patchseries further.
2015-02-05target-arm: Make arm_current_el() return sensible values for M profilePeter Maydell1-0/+4
Although M profile doesn't have the same concept of exception level as A profile, it does have a notion of privileged versus not, which we currently track in the privmode TB flag. Support returning this information if arm_current_el() is called on an M profile core, so that we can identify the correct MMU index to use (and put the MMU index in the TB flags) without having to special-case M profile. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
2015-02-05target-arm: Split NO_MIGRATE into ALIAS and NO_RAWPeter Maydell1-4/+11
We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1422282372-13735-2-git-send-email-peter.maydell@linaro.org [PMM: changed ARM_CP_NO_MIGRATE to ARM_CP_ALIAS on new SP_EL1 and SP_EL2 reginfo stanzas since there was a (semantic) merge conflict with the patchset that added those]
2015-01-20exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell1-2/+0
The TARGET_HAS_ICE #define is intended to indicate whether a target-* guest CPU implementation supports the breakpoint handling. However, all our guest CPUs have that support (the only two which do not define TARGET_HAS_ICE are unicore32 and openrisc, and in both those cases the bp support is present and the lack of the #define is just a bug). So remove the #define entirely: all new guest CPU support should include breakpoint handling as part of the basic implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1420484960-32365-1-git-send-email-peter.maydell@linaro.org
2014-12-11target-arm: make MAIR0/1 bankedGreg Bellows1-1/+20
Added CP register info entries for the ARMv7 MAIR0/1 secure banks. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-26-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make c13 cp regs banked (FCSEIDR, ...)Fabian Aggeler1-5/+31
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-25-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make VBAR bankedGreg Bellows1-1/+9
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) VBAR has a secure and a non-secure instance, which are mapped to VBAR_EL1 and VBAR_EL3. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-24-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make PAR bankedFabian Aggeler1-1/+9
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) PAR has a secure and a non-secure instance. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-23-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make IFAR/DFAR bankedFabian Aggeler1-1/+18
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFAR and DFAR have a secure and a non-secure instance. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-22-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make DFSR bankedFabian Aggeler1-1/+9
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DFSR has a secure and a non-secure instance. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-21-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make IFSR bankedFabian Aggeler1-1/+9
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFSR has a secure and a non-secure instance. Adds IFSR32_EL2 definition and storage. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-20-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make DACR bankedFabian Aggeler1-2/+11
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DACR has a secure and a non-secure instance. Adds definition for DACR32_EL2. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-19-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make TTBCR bankedFabian Aggeler1-3/+8
Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-18-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make TTBR0/1 bankedFabian Aggeler1-2/+18
Adds secure and non-secure bank register suport for TTBR0 and TTBR1. Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as well as a CP register definition for TTBR0_EL3. Added a union containing both EL based array fields and secure and non-secure fields mapped to them. Updated accesses to use A32_BANKED_CURRENT_REG_GET macro. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-17-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make CSSELR bankedFabian Aggeler1-1/+9
Rename CSSELR (cache size selection register) and add secure instance (AArch32). Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-16-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler1-1/+9
Implements SCTLR_EL3 and uses secure/non-secure instance when needed. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-14-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add MVBAR supportFabian Aggeler1-0/+1
Use MVBAR register as exception vector base address for exceptions taken to CPU monitor mode. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-13-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add SDER definitionGreg Bellows1-0/+1
Added CP register defintions for SDER and SDER32_EL3 as well as cp15.sder for register storage. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-12-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add NSACR registerFabian Aggeler1-0/+1
Implements NSACR register with corresponding read/write functions for ARMv7 and ARMv8. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-11-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add secure state bit to CPREG hashPeter Maydell1-5/+20
Added additional NS-bit to CPREG hash encoding. Updated hash lookup locations to specify hash bit currently set to non-secure. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-7-git-send-email-greg.bellows@linaro.org [PMM: fix uses of ENCODE_CP_REG in kvm32.c to add extra argument] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add CPREG secure state supportFabian Aggeler1-2/+34
Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-6-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add non-secure Translation Block flagSergey Fedorov1-0/+27
This patch is based on idea found in patch at git://github.com/jowinter/qemu-trustzone.git f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by Johannes Winter <johannes.winter@iaik.tugraz.at>. The TBFLAG captures the SCR NS secure state at the time when a TB is created so the correct bank is accessed on system register accesses. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-5-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add banked register accessorsFabian Aggeler1-0/+27
If EL3 is in AArch32 state certain cp registers are banked (secure and non-secure instance). When reading or writing to coprocessor registers the following macros can be used. - A32_BANKED macros are used for choosing the banked register based on provided input security argument. This macro is used to choose the bank during translation of MRC/MCR instructions that are dependent on something other than the current secure state. - A32_BANKED_CURRENT macros are used for choosing the banked register based on current secure state. This is NOT to be used for choosing the bank used during translation as it breaks monitor mode. If EL3 is operating in AArch64 state coprocessor registers are not banked anymore. The macros use the non-secure instance (_ns) in this case, which is architecturally mapped to the AArch64 EL register. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-4-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: extend async excp maskingGreg Bellows1-14/+52
This patch extends arm_excp_unmasked() to use lookup tables for determining whether IRQ and FIQ exceptions are masked. The lookup tables are based on the ARMv8 and ARMv7 specification physical interrupt masking tables. If EL3 is using AArch64 IRQ/FIQ masking is ignored in all exception levels other than EL3 if SCR.{FIQ|IRQ} is set to 1 (routed to EL3). Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-2-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-11-04target-arm: Correct condition for taking VIRQ and VFIQPeter Maydell1-2/+2
The VIRQ and VFIQ exceptions are (as the comments say) only taken if the CPU is in Non-secure state and the IMO/FMO bits are set to enable virtualized interrupts. Correct the code to actually implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1414684132-23971-3-git-send-email-peter.maydell@linaro.org
2014-11-04target-arm: Separate out M profile cpu_exec_interrupt handlingPeter Maydell1-14/+2
The M profile cpu_exec_interrupt handling is fairly simple but does include an M profile specific oddity (disabling interrupts for certain PC values). A/R profile handling on the other hand is getting rapidly more complicated with the support for EL2 and EL3. Split the M profile code out into its own implementation of cpu_exec_interrupt to keep these two things out of each others' way. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1414684132-23971-2-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: make arm_current_el() return EL3Fabian Aggeler1-9/+20
Make arm_current_el() return EL3 for secure PL1 and monitor mode. Increase MMU modes since mmu_index is directly inferred from arm_ current_el(). Change assertion in arm_el_is_aa64() to allow EL3. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-6-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows1-12/+15
Renamed the arm_current_pl CPU function to more accurately represent that it returns the ARMv8 EL rather than ARMv7 PL. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-5-git-send-email-greg.bellows@linaro.org [PMM: fixed a minor merge resolution error in a couple of hunks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: add arm_is_secure() functionFabian Aggeler1-0/+47
arm_is_secure() function allows to determine CPU security state if the CPU implements Security Extensions/EL3. arm_is_secure_below_el3() returns true if CPU is in secure state below EL3. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-3-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: increase arrays of registers R13 & R14Fabian Aggeler1-2/+2
Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank index 7). Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-2-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring1-0/+6
Add support for handling PSCI calls in system emulation. Both version 0.1 and 0.2 of the PSCI spec are supported. Platforms can enable support by setting the "psci-conduit" QOM property on the cpus to SMC or HVC emulation and having a PSCI binding in their dtb. Signed-off-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-7-git-send-email-peter.maydell@linaro.org [PMM: made system reset/off PSCI functions power down the CPU so we obey the PSCI API requirement never to return from them; rearranged how the code is plumbed into the exception system, so that we split "is this a valid call?" from "do the call"] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-29target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias1-3/+32
This only implements the external delivery method via the GIC. Acked-by: Greg Bellows <greg.bellows@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1411718914-6608-12-git-send-email-edgar.iglesias@gmail.com [PMM: adjusted following cpu-exec refactoring] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-29target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias1-0/+10
Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1411718914-6608-11-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias1-0/+1
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1411718914-6608-10-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2024-11-19 20:14:17 +0000