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path: root/target-arm/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2014-12-11target-arm: make MAIR0/1 bankedGreg Bellows1-1/+20
2014-12-11target-arm: make c13 cp regs banked (FCSEIDR, ...)Fabian Aggeler1-5/+31
2014-12-11target-arm: make VBAR bankedGreg Bellows1-1/+9
2014-12-11target-arm: make PAR bankedFabian Aggeler1-1/+9
2014-12-11target-arm: make IFAR/DFAR bankedFabian Aggeler1-1/+18
2014-12-11target-arm: make DFSR bankedFabian Aggeler1-1/+9
2014-12-11target-arm: make IFSR bankedFabian Aggeler1-1/+9
2014-12-11target-arm: make DACR bankedFabian Aggeler1-2/+11
2014-12-11target-arm: make TTBCR bankedFabian Aggeler1-3/+8
2014-12-11target-arm: make TTBR0/1 bankedFabian Aggeler1-2/+18
2014-12-11target-arm: make CSSELR bankedFabian Aggeler1-1/+9
2014-12-11target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler1-1/+9
2014-12-11target-arm: add MVBAR supportFabian Aggeler1-0/+1
2014-12-11target-arm: add SDER definitionGreg Bellows1-0/+1
2014-12-11target-arm: add NSACR registerFabian Aggeler1-0/+1
2014-12-11target-arm: add secure state bit to CPREG hashPeter Maydell1-5/+20
2014-12-11target-arm: add CPREG secure state supportFabian Aggeler1-2/+34
2014-12-11target-arm: add non-secure Translation Block flagSergey Fedorov1-0/+27
2014-12-11target-arm: add banked register accessorsFabian Aggeler1-0/+27
2014-12-11target-arm: extend async excp maskingGreg Bellows1-14/+52
2014-11-04target-arm: Correct condition for taking VIRQ and VFIQPeter Maydell1-2/+2
2014-11-04target-arm: Separate out M profile cpu_exec_interrupt handlingPeter Maydell1-14/+2
2014-10-24target-arm: make arm_current_el() return EL3Fabian Aggeler1-9/+20
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows1-12/+15
2014-10-24target-arm: add arm_is_secure() functionFabian Aggeler1-0/+47
2014-10-24target-arm: increase arrays of registers R13 & R14Fabian Aggeler1-2/+2
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring1-0/+6
2014-09-29target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias1-3/+32
2014-09-29target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias1-0/+10
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias1-0/+1
2014-09-29target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias1-0/+1
2014-09-29target-arm: A64: Emulate the HVC insnEdgar E. Iglesias1-0/+1
2014-09-29target-arm: Don't take interrupts targeting lower ELsEdgar E. Iglesias1-0/+7
2014-09-29target-arm: Break out exception masking to a separate funcEdgar E. Iglesias1-0/+15
2014-09-29target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias1-0/+7
2014-09-29target-arm: Add SCR_EL3Edgar E. Iglesias1-1/+18
2014-09-29target-arm: Add HCR_EL2Edgar E. Iglesias1-0/+36
2014-09-29target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell1-0/+9
2014-09-29target-arm: Implement setting guest breakpointsPeter Maydell1-0/+1
2014-09-12target-arm: Implement setting of watchpointsPeter Maydell1-0/+2
2014-08-29target-arm: Implement pmccntr_sync functionAlistair Francis1-0/+11
2014-08-29target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis1-2/+3
2014-08-29target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis1-1/+1
2014-08-29target-arm: Fix regression that disabled VFP for ARMv5 CPUsPeter Maydell1-1/+8
2014-08-19target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell1-0/+21
2014-08-19target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell1-0/+21
2014-08-19target-arm: Set PSTATE.SS correctly on exception return from AArch64Peter Maydell1-0/+61
2014-08-19target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell1-2/+10
2014-08-04target-arm: Add FAR_EL2 and 3Edgar E. Iglesias1-1/+1
2014-08-04target-arm: Add ESR_EL2 and 3Edgar E. Iglesias1-1/+1
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