index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-arm
/
cpu.h
Age
Commit message (
Expand
)
Author
Files
Lines
2014-12-11
target-arm: make MAIR0/1 banked
Greg Bellows
1
-1
/
+20
2014-12-11
target-arm: make c13 cp regs banked (FCSEIDR, ...)
Fabian Aggeler
1
-5
/
+31
2014-12-11
target-arm: make VBAR banked
Greg Bellows
1
-1
/
+9
2014-12-11
target-arm: make PAR banked
Fabian Aggeler
1
-1
/
+9
2014-12-11
target-arm: make IFAR/DFAR banked
Fabian Aggeler
1
-1
/
+18
2014-12-11
target-arm: make DFSR banked
Fabian Aggeler
1
-1
/
+9
2014-12-11
target-arm: make IFSR banked
Fabian Aggeler
1
-1
/
+9
2014-12-11
target-arm: make DACR banked
Fabian Aggeler
1
-2
/
+11
2014-12-11
target-arm: make TTBCR banked
Fabian Aggeler
1
-3
/
+8
2014-12-11
target-arm: make TTBR0/1 banked
Fabian Aggeler
1
-2
/
+18
2014-12-11
target-arm: make CSSELR banked
Fabian Aggeler
1
-1
/
+9
2014-12-11
target-arm: add SCTLR_EL3 and make SCTLR banked
Fabian Aggeler
1
-1
/
+9
2014-12-11
target-arm: add MVBAR support
Fabian Aggeler
1
-0
/
+1
2014-12-11
target-arm: add SDER definition
Greg Bellows
1
-0
/
+1
2014-12-11
target-arm: add NSACR register
Fabian Aggeler
1
-0
/
+1
2014-12-11
target-arm: add secure state bit to CPREG hash
Peter Maydell
1
-5
/
+20
2014-12-11
target-arm: add CPREG secure state support
Fabian Aggeler
1
-2
/
+34
2014-12-11
target-arm: add non-secure Translation Block flag
Sergey Fedorov
1
-0
/
+27
2014-12-11
target-arm: add banked register accessors
Fabian Aggeler
1
-0
/
+27
2014-12-11
target-arm: extend async excp masking
Greg Bellows
1
-14
/
+52
2014-11-04
target-arm: Correct condition for taking VIRQ and VFIQ
Peter Maydell
1
-2
/
+2
2014-11-04
target-arm: Separate out M profile cpu_exec_interrupt handling
Peter Maydell
1
-14
/
+2
2014-10-24
target-arm: make arm_current_el() return EL3
Fabian Aggeler
1
-9
/
+20
2014-10-24
target-arm: rename arm_current_pl to arm_current_el
Greg Bellows
1
-12
/
+15
2014-10-24
target-arm: add arm_is_secure() function
Fabian Aggeler
1
-0
/
+47
2014-10-24
target-arm: increase arrays of registers R13 & R14
Fabian Aggeler
1
-2
/
+2
2014-10-24
target-arm: add emulation of PSCI calls for system emulation
Rob Herring
1
-0
/
+6
2014-09-29
target-arm: Add support for VIRQ and VFIQ
Edgar E. Iglesias
1
-3
/
+32
2014-09-29
target-arm: Add IRQ and FIQ routing to EL2 and 3
Edgar E. Iglesias
1
-0
/
+10
2014-09-29
target-arm: A64: Emulate the SMC insn
Edgar E. Iglesias
1
-0
/
+1
2014-09-29
target-arm: Add a Hypervisor Trap exception type
Edgar E. Iglesias
1
-0
/
+1
2014-09-29
target-arm: A64: Emulate the HVC insn
Edgar E. Iglesias
1
-0
/
+1
2014-09-29
target-arm: Don't take interrupts targeting lower ELs
Edgar E. Iglesias
1
-0
/
+7
2014-09-29
target-arm: Break out exception masking to a separate func
Edgar E. Iglesias
1
-0
/
+15
2014-09-29
target-arm: A64: Refactor aarch64_cpu_do_interrupt
Edgar E. Iglesias
1
-0
/
+7
2014-09-29
target-arm: Add SCR_EL3
Edgar E. Iglesias
1
-1
/
+18
2014-09-29
target-arm: Add HCR_EL2
Edgar E. Iglesias
1
-0
/
+36
2014-09-29
target-arm: Don't handle c15_cpar changes via tb_flush()
Peter Maydell
1
-0
/
+9
2014-09-29
target-arm: Implement setting guest breakpoints
Peter Maydell
1
-0
/
+1
2014-09-12
target-arm: Implement setting of watchpoints
Peter Maydell
1
-0
/
+2
2014-08-29
target-arm: Implement pmccntr_sync function
Alistair Francis
1
-0
/
+11
2014-08-29
target-arm: Implement PMCCNTR_EL0 and related registers
Alistair Francis
1
-2
/
+3
2014-08-29
target-arm: Make the ARM PMCCNTR register 64-bit
Alistair Francis
1
-1
/
+1
2014-08-29
target-arm: Fix regression that disabled VFP for ARMv5 CPUs
Peter Maydell
1
-1
/
+8
2014-08-19
target-arm: Implement ARMv8 single-stepping for AArch32 code
Peter Maydell
1
-0
/
+21
2014-08-19
target-arm: Implement ARMv8 single-step handling for A64 code
Peter Maydell
1
-0
/
+21
2014-08-19
target-arm: Set PSTATE.SS correctly on exception return from AArch64
Peter Maydell
1
-0
/
+61
2014-08-19
target-arm: Don't allow AArch32 to access RES0 CPSR bits
Peter Maydell
1
-2
/
+10
2014-08-04
target-arm: Add FAR_EL2 and 3
Edgar E. Iglesias
1
-1
/
+1
2014-08-04
target-arm: Add ESR_EL2 and 3
Edgar E. Iglesias
1
-1
/
+1
[next]