index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-arm
/
cpu.c
Age
Commit message (
Expand
)
Author
Files
Lines
2012-07-12
target-arm: Extend feature flags to 64 bits
Peter Maydell
1
-1
/
+1
2012-07-12
target-arm: Implement privileged-execute-never (PXN)
Peter Maydell
1
-0
/
+4
2012-06-20
target-arm: Remove ARM_CPUID_* macros
Peter Maydell
1
-25
/
+25
2012-06-20
target-arm: Convert final ID registers
Peter Maydell
1
-2
/
+0
2012-06-20
target-arm: Convert MPIDR
Peter Maydell
1
-0
/
+2
2012-06-20
target-arm: Convert cp15 cache ID registers
Peter Maydell
1
-2
/
+0
2012-06-20
target-arm: Convert cp15 crn=0 crm={1,2} feature registers
Peter Maydell
1
-14
/
+0
2012-06-20
target-arm: Convert cp15 crn=1 registers
Peter Maydell
1
-1
/
+6
2012-06-20
target-arm: Convert cp15 crn=9 registers
Peter Maydell
1
-0
/
+34
2012-06-20
target-arm: Convert cp15 crn=6 registers
Peter Maydell
1
-0
/
+10
2012-06-20
target-arm: convert cp15 crn=7 registers
Peter Maydell
1
-0
/
+19
2012-06-20
target-arm: Convert cp15 crn=15 registers
Peter Maydell
1
-2
/
+38
2012-06-20
target-arm: Convert cp15 crn=2 registers
Peter Maydell
1
-1
/
+0
2012-06-20
target-arm: Convert performance monitor registers
Peter Maydell
1
-4
/
+0
2012-06-20
target-arm: Add register_cp_regs_for_features()
Peter Maydell
1
-0
/
+2
2012-06-20
target-arm: initial coprocessor register framework
Peter Maydell
1
-0
/
+41
2012-06-20
target-arm: Fix 11MPCore cache type register value
Peter Maydell
1
-1
/
+1
2012-04-27
target-arm: Move A9 config_base_address reset value to ARMCPU
Peter Maydell
1
-3
/
+1
2012-04-27
target-arm: Change cpu_arm_init() return type to ARMCPU
Andreas Färber
1
-1
/
+1
2012-04-21
target-arm: Move reset handling to arm_cpu_reset
Peter Maydell
1
-3
/
+91
2012-04-21
target-arm: Move cache ID register setup to cpu specific init fns
Peter Maydell
1
-0
/
+11
2012-04-21
target-arm: Move feature register setup to per-CPU init fns
Peter Maydell
1
-0
/
+94
2012-04-21
target-arm: Move SCTLR reset value setup to per cpu init fns
Peter Maydell
1
-0
/
+23
2012-04-21
target-arm: Move CTR setup to per cpu init fns
Peter Maydell
1
-0
/
+22
2012-04-21
target-arm: Move MVFR* setup to per cpu init fns
Peter Maydell
1
-0
/
+14
2012-04-21
target-arm: Move FPSID config to cpu init fns
Peter Maydell
1
-0
/
+9
2012-04-21
target-arm: Move feature bit settings to CPU init fns
Peter Maydell
1
-0
/
+132
2012-04-21
target-arm: Add QOM subclasses for each ARM cpu implementation
Peter Maydell
1
-1
/
+225
2012-03-29
target-arm: Minimalistic CPU QOM'ification
Andreas Färber
1
-0
/
+60