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path: root/target-arm/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2016-02-18target-arm: Add the pmceid0 and pmceid1 registersAlistair Francis1-0/+2
2016-02-11target-arm: Implement checking of fired watchpointSergey Fedorov1-0/+1
2016-02-03target-arm: Don't report presence of EL2 if it doesn't existPeter Maydell1-0/+9
2016-01-27gdb: provide the name of the architecture in the target.xmlDavid Hildenbrand1-0/+12
2016-01-21target-arm: Implement cpu_get_phys_page_attrs_debugPeter Maydell1-1/+1
2016-01-21target-arm: Implement asidx_from_attrsPeter Maydell1-0/+1
2016-01-21target-arm: Add QOM property for Secure memory regionPeter Maydell1-0/+32
2016-01-18target-arm: Clean up includesPeter Maydell1-0/+1
2016-01-15target-arm: support QMP dump-guest-memoryAndrew Jones1-0/+2
2016-01-13error: Strip trailing '\n' from error string arguments (again)Markus Armbruster1-1/+1
2015-12-17target-arm: raise exception on misaligned LDREX operandsAndrew Baumann1-0/+1
2015-10-09qdev: Protect device-list-properties against broken devicesMarkus Armbruster1-0/+11
2015-09-07target-arm: Refactor CPU affinity handlingPavel Fedin1-1/+1
2015-09-07arm: Remove hw_error() usages.Peter Crosthwaite1-2/+2
2015-09-07arm: cpu: assert() on no-EL2 virt IRQ error condition.Peter Crosthwaite1-4/+1
2015-08-13target-arm: Add the AArch64 view of the Secure physical timerPeter Maydell1-0/+2
2015-08-13target-arm: Add debug check for mismatched cpreg resetsPeter Maydell1-0/+23
2015-08-13target-arm: Add the Hypervisor timerEdgar E. Iglesias1-0/+2
2015-07-09disas: arm: QOMify target specific disas setupPeter Crosthwaite1-0/+35
2015-07-09cpu: Change cpu_exec_init() arg to cpu, not envPeter Crosthwaite1-1/+1
2015-07-09cpu: Add Error argument to cpu_exec_init()Bharata B Rao1-1/+1
2015-06-22Include qapi/qmp/qerror.h exactly where neededMarkus Armbruster1-1/+0
2015-06-19target-arm: Add support for Cortex-R5Peter Crosthwaite1-0/+38
2015-06-19target-arm: Add registers for PMSAv7Peter Crosthwaite1-0/+6
2015-06-19target-arm/helper.c: define MPUIR registerPeter Crosthwaite1-0/+18
2015-06-19target-arm: Do not reset sysregs marked as ALIASSergey Fedorov1-1/+1
2015-06-19target-arm: Add the Cortex-M4 CPUAurelio C. Remonda1-0/+11
2015-06-15arm: Add has-mpu propertyPeter Crosthwaite1-0/+13
2015-06-15target-arm: Add the THUMB_DSP featureAurelio C. Remonda1-0/+4
2015-06-15target-arm: Use the kernel's idea of MPIDR if we're using KVMPavel Fedin1-0/+12
2015-05-29target-arm: Update interrupt handling to use target ELGreg Bellows1-20/+41
2015-05-29target-arm: Move setting of exception info into tlb_fillPeter Maydell1-0/+17
2015-04-26target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabledSergey Fedorov1-1/+2
2015-04-26target-arm: rename c1_coproc to cpacr_el1Sergey Fedorov1-2/+2
2015-02-13target-arm: Add CPU property to disable AArch64Greg Bellows1-1/+4
2015-02-05target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64Pranavkumar Sawargaonkar1-0/+24
2015-02-05target-arm: Change reset to highest available ELGreg Bellows1-1/+8
2014-12-22target-arm: add cpu feature EL3 to CPUs with Security ExtensionsFabian Aggeler1-0/+4
2014-12-22target-arm: Add ARMCPU secure propertyGreg Bellows1-0/+23
2014-12-22target-arm: Add feature unset functionGreg Bellows1-0/+5
2014-12-11target-arm: make IFAR/DFAR bankedFabian Aggeler1-1/+1
2014-12-11target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler1-2/+6
2014-11-04target-arm: Separate out M profile cpu_exec_interrupt handlingPeter Maydell1-10/+39
2014-10-24target-arm: Correct sense of the DCZID DZP bitPeter Maydell1-2/+2
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring1-3/+7
2014-10-24target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring1-1/+1
2014-10-24target-arm: add powered off cpu stateRob Herring1-1/+7
2014-10-06gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell1-0/+1
2014-09-29target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias1-11/+36
2014-09-29target-arm: Break out exception masking to a separate funcEdgar E. Iglesias1-5/+2
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