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2014-06-24Add support for the arm breakpoint syscallHunter Laux1-0/+4
OABI arm used a software interrupt(0xef9f0001) for breakpoints. Since 2005 gdb has used the break instruction(0xe7f001f0) for EABI. Apparently Steel Bank Common Lisp still uses the swi instruction. This is the kernel implementation: http://lxr.free-electrons.com/source/arch/arm/kernel/traps.c#L598 Signed-off-by: Hunter Laux <hunterlaux@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-23tcg-ppc: Merge cache-utils into the backendRichard Henderson1-3/+0
As a "utility", it only supported ppc, and in a way that other tcg backends provided directly in tcg-target.h. Removing this disparity is easier now that the two ppc backends are merged. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-06-23qemu/osdep: Remove the need for qemu_init_auxvalRichard Henderson1-1/+0
Instead of getting backup auxv data from the env pointer given to main, read it from /proc/self/auxv. We can do this at any time, so we're not tied to any ordering wrt a call to qemu_init_auxval from main. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-06-16target-ppc: Store Quadword Conditional Drops Size BitTom Musta1-1/+1
The size and register information are encoded into the reserve_info field of CPU state in the store conditional translation code. Specifically, the size is shifted left by 5 bits (see target-ppc/translate.c gen_conditional_store). The user-mode store conditional code erroneously extracts the size by ANDing with a 4 bit mask; this breaks if size >= 16. Eliminate the mask to make the extraction of size mirror its encoding. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Allow little-endian user mode.Doug Kwan1-1/+7
This allows running PPC64 little-endian in user mode if target is configured that way. In PPC64 LE user mode we set MSR.LE during initialization. Signed-off-by: Doug Kwan <dougkwan@google.com> Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-21target-i386: fix segment flags for SMM and VM86 modePaolo Bonzini1-1/+1
With the next patch, these need to be correct or VM86 tasks have the wrong CPL. The flags are basically what the Intel VMX documentation say is mandatory for entry into a VM86 guest. For consistency, SMM ought to have the same flags except with CPL=0. Tested-by: Kevin O'Connor <kevin@koconnor.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13target-i386: the x86 CPL is stored in CS.selector - auto update hflags ↵Kevin O'Connor1-2/+0
accordingly. Instead of manually calling cpu_x86_set_cpl() when the CPL changes, check for CPL changes on calls to cpu_x86_load_seg_cache(R_CS). Every location that called cpu_x86_set_cpl() also called cpu_x86_load_seg_cache(R_CS), so cpu_x86_set_cpl() is no longer required. This fixes the SMM handler code as it was not setting/restoring the CPL level manually. Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-02linux-user: remove configure option for setting uname releaseRiku Voipio1-1/+1
--enable-uname-release was a rather heavyweight hammer, as it allows providing values less that UNAME_MINIMUM_RELEASE. Also, it affects all built linux-user targets, which in most cases is not what user wants. Now that we have UNAME_MINIMUM_RELEASE for all linux-user platforms, we can drop --enable-uname-release and the related CONFIG_UNAME_RELEASE define. Users can still override the variable with QEMU_UNAME=2.6.32 or -r command line option. If distributors need to update a minimum version for a specific target, it can be done by updating UNAME_MINIMUM_RELEASE. Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2014-04-17target-arm: Define exception record for AArch64 exceptionsPeter Maydell1-32/+24
For AArch32 exceptions, the only information provided about the cause of an exception is the individual exception type (data abort, undef, etc), which we store in cs->exception_index. For AArch64, the CPU provides much more detail about the cause of the exception, which can be found in the syndrome register. Create a set of fields in CPUARMState which must be filled in whenever an exception is raised, so that exception entry can correctly fill in the syndrome register for the guest. This includes the information which in AArch32 appears in the DFAR and IFAR (fault address registers) and the DFSR and IFSR (fault status registers) for data aborts and prefetch aborts, since if we end up taking the MMU fault to AArch64 rather than AArch32 this will need to end up in different system registers. This patch does a refactoring which moves the setting of the AArch32 DFAR/DFSR/IFAR/IFSR from the point where the exception is raised to the point where it is taken. (This is no change for cores with an MMU, retains the existing clearly incorrect behaviour for ARM946 of trashing the MP access permissions registers which share the c5_data and c5_insn state fields, and has no effect for v7M because we don't implement its MPU fault status or address registers.) As a side effect of the cleanup we fix a bug in the AArch64 linux-user mode code where we were passing a 64 bit fault address through the 32 bit c6_data/c6_insn fields: it now goes via the always-64-bit exception.vaddress. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber1-40/+40
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13exec: Change cpu_breakpoint_{insert,remove{,_by_ref,_all}} argumentAndreas Färber1-1/+1
Use CPUState. Allows to clean up CPUArchState in gdbstub. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13exec: Change cpu_watchpoint_{insert,remove{,_by_ref,_all}} argumentAndreas Färber1-2/+3
Use CPUState. This lets us drop a few local env usages. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber1-2/+2
Most targets were using offsetof(CPUFooState, breakpoints) to determine how much of CPUFooState to clear on reset. Use the next field after CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move watchpoint fields from CPU_COMMON to CPUStateAndreas Färber1-2/+3
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move opaque field from CPU_COMMON to CPUStateAndreas Färber1-3/+3
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-10Merge remote-tracking branch 'remotes/riku/linux-user-for-upstream' into stagingPeter Maydell1-0/+4
* remotes/riku/linux-user-for-upstream: linux-user: set minimum kernel version to 2.6.32 linux-user: correct handling of break exception for MIPS linux-user: translate signal number on return from sigtimedwait linux-user: Implement sendmmsg syscall linux-user: Fix getresuid, getresgid if !USE_UID16 linux-user: Don't use UID16 on AArch64 linux-user: AArch64: Implement SA_RESTORER for signal handlers linux-user/signal.c: Fix AArch64 big-endian FP register restore Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-05target-ppc: Add Store Quadword ConditionalTom Musta1-1/+17
This patch adds the Store Quadword Conditionl (stqcx.) instruction which is introduced in Power ISA 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> [agraf: fix compile error when !TARGET_PPC64] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-03linux-user: correct handling of break exception for MIPSPetar Jovanovic1-0/+4
Exception with break instruction has not been correctly propagated as SIGTRAP. This resolves crash issues with examples that use break instruction on MIPS. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2014-02-20linux-user: AArch64: Fix exclusive store of the zero registerJanne Grunau1-2/+4
Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08target-arm: A64: support for ld/st/cl exclusiveMichael Matz1-3/+124
This implement exclusive loads/stores for aarch64 along the lines of arm32 and ppc implementations. The exclusive load remembers the address and loaded value. The exclusive store throws an an exception which uses those values to check for equality in a proper exclusive region. This is not actually the architecture mandated semantics (for either AArch32 or AArch64) but it is close enough for typical guest code sequences to work correctly, and saves us from having to monitor all guest stores. It's fairly easy to come up with test cases where we don't behave like hardware - we don't for example model cache line behaviour. However in the common patterns this works, and the existing 32 bit ARM exclusive access implementation has the same limitations. AArch64 also implements new acquire/release loads/stores (which may be either exclusive or non-exclusive). These imposes extra ordering constraints on memory operations (ie they act as if they have an implicit barrier built into them). As TCG is single-threaded all our barriers are no-ops, so these just behave like normal loads and stores. Signed-off-by: Michael Matz <matz@suse.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: Widen exclusive-access support struct fields to 64 bitsPeter Maydell1-10/+15
In preparation for adding support for A64 load/store exclusive instructions, widen the fields in the CPU state struct that deal with address and data values for exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32 exclusive accesses will be generally separate there are some odd theoretical corner cases (eg you should be able to do the exclusive load in AArch32, take an exception to AArch64 and successfully do the store exclusive there), and it's also easier to reason about. The changes in semantics for the variables are: exclusive_addr -> extended to 64 bits; -1ULL for "monitor lost", otherwise always < 2^32 for AArch32 exclusive_val -> extended to 64 bits. 64 bit exclusives in AArch32 now use the high half of exclusive_val instead of a separate exclusive_high exclusive_high -> is no longer used in AArch32; extended to 64 bits as it will be needed for AArch64's pair-of-64-bit-values exclusives. exclusive_test -> extended to 64 bits, as it is an address. Since this is a linux-user-only field, in arm-linux-user it will always have the top 32 bits zero. exclusive_info -> stays 32 bits, as it is neither data nor address, but simply holds register indexes etc. AArch64 will be able to fit all its information into 32 bits as well. Note that the refactoring of gen_store_exclusive() coincidentally fixes a minor bug where ldrexd would incorrectly update the first CPU register even if the load for the second register faulted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-arm: Widen thread-local register state fields to 64 bitsPeter Maydell1-1/+1
The common pattern for system registers in a 64-bit capable ARM CPU is that when in AArch32 the cp15 register is a view of the bottom 32 bits of the 64-bit AArch64 system register; writes in AArch32 leave the top half unchanged. The most natural way to model this is to have the state field in the CPU struct be a 64 bit value, and simply have the AArch32 TCG code operate on a pointer to its lower half. For aarch64-linux-user the only registers we need to share like this are the thread-local-storage ones. Widen their fields to 64 bits and provide the 64 bit reginfo struct to make them visible in AArch64 state. Note that minor cleanup of the AArch64 system register encoding space means We can share the TPIDR_EL1 reginfo but need split encodings for TPIDR_EL0 and TPIDRRO_EL0. Since we're touching almost every line in QEMU that uses the c13_tls* fields in this patch anyway, we take the opportunity to rename them in line with the standard ARM architectural names for these registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-11-30linux-user: Use qemu_getauxval for AT_EXECFDRichard Henderson1-26/+6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-30util: Use qemu_getauxval in linux qemu_cache_utils_initRichard Henderson1-1/+1
With this we no longer pass down envp, and thus all systems can have the same void prototype. So also eliminate a useless thunk. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-30osdep: Create qemu_getauxval and qemu_init_auxvalRichard Henderson1-0/+1
Abstract away dependence on a system implementation of getauxval. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-07cpu: Drop cpu_model_str from CPU_COMMONAndreas Färber1-2/+2
Since this is only read in cpu_copy() and linux-user has a global cpu_model, drop the field from generic code. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-10-07cpu: Move cpu_copy() into linux-userAndreas Färber1-0/+31
It is only used there and is deemed very fragile if not incorrect in its current memcpy() form. Moving it into linux-user will allow to move parts into target_cpu.h headers and only copy what the ABI mandates. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-09-24linux-user: Check type of microMIPS break instructionKwok Cheung Yeung1-21/+35
microMIPS instructions that cause breakpoint exceptions come in 16-bit and 32-bit variants. When handling exceptions caused by such instructions, the instruction type needs to be taken into account when extracting the break code. The code has also been restructured for better clarity. Signed-off-by: Kwok Cheung Yeung <kcy@codesourcery.com> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2013-09-24linux-user: add support of binfmt_misc 'O' flagLaurent Vivier1-1/+31
The binfmt_misc module can calculate the credentials and security token according to the binary instead of to the interpreter if the 'C' flag is enabled. To be able to execute non-readable binaries, this flag implies 'O' flag. When 'O' flag is enabled, bintfmt_misc opens the file for reading and pass the file descriptor to the interpreter. References: linux/Documentation/binfmt_misc.txt ['O' and 'C' description] linux/fs/binfmt_misc.c linux/fs/binfmt_elf.c [ AT_EXECFD usage ] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2013-09-24mips-linux-user: Adjust names in mips_syscall_argsRichard Henderson1-2/+2
The name field of MIPS_SYS isn't actually used; it's just documentation. But adjust the umount entries to match mips/syscall_nr.h anyway. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2013-09-10linux-user: Add AArch64 supportAlexander Graf1-0/+16
This patch adds support for AArch64 in all the small corners of linux-user (primarily in image loading and startup code). Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-22-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-11-git-send-email-john.rigby@linaro.org [PMM: * removed some unnecessary #defines from syscall.h * catch attempts to use a 32 bit only cpu with aarch64-linux-user * termios stuff moved into its own patch * we specify our minimum uname version here now ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-09-10linux-user: Allow targets to specify a minimum uname releasePeter Maydell1-0/+2
For newer target architectures, glibc can be picky about the kernel version: for example, it will not run on an aarch64 system unless the kernel reports itself as at least 3.8.0. Accommodate this by enhancing the existing support for faking the kernel version so that each target can optionally specify a minimum version: if the user doesn't force a specific fake version then we will override with the minimum required version only if the real host kernel version is insufficient. Use this facility to let aarch64 report a minimum of 3.8.0. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-21-git-send-email-peter.maydell@linaro.org
2013-09-10linux-user: Add cpu loop for AArch64Peter Maydell1-0/+82
Add the main linux-user cpu loop for AArch64. Since AArch64 has a different system call interface, doesn't need to worry about FPA emulation and may in the future keep the prefetch/data abort information in different system registers, it's simplest just to use a completely separate loop from the 32 bit ARM target, rather than peppering it with ifdefs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-14-git-send-email-peter.maydell@linaro.org
2013-09-03cpu: Use QTAILQ for CPU listAndreas Färber1-3/+7
Introduce CPU_FOREACH(), CPU_FOREACH_SAFE() and CPU_NEXT() shorthand macros. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29linux-user: correct argument number for sys_mremap and sys_splicePetar Jovanovic1-2/+2
sys_mremap missed 5th argument (new_address), which caused examples that remap to a specific address to fail. sys_splice missed 5th and 6th argument which caused different examples to fail. This change has an effect on MIPS target only. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-26linux-user: Avoid redundant ENV_GET_CPU()Andreas Färber1-1/+1
This fixes a mismerge in 874ec3c5b3821bb964f9f37b2f930f2a9ce51652. Acked-by: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-25Merge remote-tracking branch 'riku/linux-user-for-upstream' into stagingAnthony Liguori1-49/+44
* riku/linux-user-for-upstream: (21 commits) linux-user: Handle compressed ISA encodings when processing MIPS exceptions linux-user: Unlock mmap_lock when resuming guest from page_unprotect linux-user: Reset copied CPUs in cpu_copy() always linux-user: Fix epoll on ARM hosts linux-user: fix segmentation fault passing with h2g(x) != x linux-user: Fix pipe syscall return for SPARC linux-user: Fix target_stat and target_stat64 for OpenRISC linux-user: Avoid conditional cpu_reset() configure: Make NPTL non-optional linux-user: Enable NPTL for x86-64 linux-user: Add i386 TLS setter linux-user: Clean up handling of clone() argument order linux-user: Add missing 'break' in i386 get_thread_area syscall linux-user: Enable NPTL for m68k linux-user: Enable NPTL for SPARC targets linux-user: Enable NPTL for OpenRISC linux-user: Move includes of target-specific headers to end of qemu.h configure: Enable threading for unicore32-linux-user configure: Enable threading on all ppc and mips linux-user targets configure: Don't say target_nptl="no" if there is no linux-user target ... Conflicts: linux-user/main.c Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-23linux-user: Handle compressed ISA encodings when processing MIPS exceptionsKwok Cheung Yeung1-3/+43
Decode trap instructions during the handling of an EXCP_BREAK or EXCP_TRAP according to the current ISA mode. Signed-off-by: Kwok Cheung Yeung <kcy@codesourcery.com> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2013-07-23gdbstub: Change gdb_handlesig() argument to CPUStateAndreas Färber1-16/+19
Prepares for changing GDBState::c_cpu to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-22linux-user: Avoid conditional cpu_reset()Andreas Färber1-2/+0
Some CPUs reset as part of cpu_init(), some others were reset afterwards, some not at all. While some targets didn't implement a cpu_[state_]reset() function, QOM cpu_reset() is always available. There's nothing wrong with resetting twice on startup, so drop the #ifdef. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2013-07-22configure: Make NPTL non-optionalPeter Maydell1-43/+0
Now all linux-user targets support building with NPTL, we can make it mandatory. This is a good idea because: * NPTL is no longer new and experimental; it is completely standard * in practice, linux-user without NPTL is nearly useless for binaries built against non-ancient glibc * it allows us to delete the rather untested code for handling the non-NPTL configuration Note that this patch leaves the CONFIG_USE_NPTL ifdefs in the bsd-user codebase alone. This makes no change for bsd-user, since our configure test for NPTL had a "#include <linux/futex.h>" which means bsd-user would never have been compiled with CONFIG_USE_NPTL defined, and it still is not. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2013-07-19linux-user: declare sys_futex to have 6 argumentsPetar Jovanovic1-1/+1
sys_futex has 6 arguments, and all of these need to be copied. Fix incorrect declaration in the mips_syscall_args array. This change fixes the cases where the 5th and 6th arguments have non-zero value and have importance. An example is a Linux implementation of pthread_cond_wait() function. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-07-09log: Change log_cpu_state[_mask]() argument to CPUStateAndreas Färber1-2/+3
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is no longer needed. Add documentation and make the functions available through qemu/log.h outside NEED_CPU_H to allow use in qom/cpu.c. Moving them to qom/cpu.h was not yet possible due to convoluted include paths, so that some devices grow an implicit and unneeded dependency on qom/cpu.h for now. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Reviewed-by: Richard Henderson <rth@twiddle.net> [AF: Simplified mb_cpu_do_interrupt() and do_interrupt_all() changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09linux-user: Change thread_env to CPUStateAndreas Färber1-5/+5
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09cpu: Make first_cpu and next_cpu CPUStateAndreas Färber1-5/+3
Move next_cpu from CPU_COMMON to CPUState. Move first_cpu variable to qom/cpu.h. gdbstub needs to use CPUState::env_ptr for now. cpu_copy() no longer needs to save and restore cpu_next. Acked-by: Paolo Bonzini <pbonzini@redhat.com> [AF: Rebased, simplified cpu_copy()] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber1-15/+23
Make cpustats monitor command available unconditionally. Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec() arguments to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-28cpu: Change cpu_exit() argument to CPUStateAndreas Färber1-1/+1
It no longer depends on CPUArchState, so move it to qom/cpu.c. Prepares for changing GDBState::c_cpu to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-14main: use TARGET_ARCH only for the target-specific #definePaolo Bonzini1-3/+3
Everything else needs to match the executable name, which is TARGET_NAME. Before: $ sh4eb-linux-user/qemu-sh4eb --help usage: qemu-sh4 [options] program [arguments...] Linux CPU emulator (compiled for sh4 emulation) After: $ sh4eb-linux-user/qemu-sh4eb --help usage: qemu-sh4eb [options] program [arguments...] Linux CPU emulator (compiled for sh4eb emulation) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1370349928-20419-5-git-send-email-pbonzini@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-05-02target-i386: Replace cpuid_*features fields with a feature word arrayEduardo Habkost1-2/+2
This replaces the feature-bit fields on both X86CPU and x86_def_t structs with an array. With this, we will be able to simplify code that simply does the same operation on all feature words (e.g. kvm_check_features_against_host(), filter_features_for_kvm(), add_flagname_to_bitmaps(), CPU feature-bit property lookup/registration, and the proposed "feature-words" property) The following field replacements were made on X86CPU and x86_def_t: (cpuid_)features -> features[FEAT_1_EDX] (cpuid_)ext_features -> features[FEAT_1_ECX] (cpuid_)ext2_features -> features[FEAT_8000_0001_EDX] (cpuid_)ext3_features -> features[FEAT_8000_0001_ECX] (cpuid_)ext4_features -> features[FEAT_C000_0001_EDX] (cpuid_)kvm_features -> features[FEAT_KVM] (cpuid_)svm_features -> features[FEAT_SVM] (cpuid_)7_0_ebx_features -> features[FEAT_7_0_EBX] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-11linux-user: Fix layout of usage table to account for option textPeter Maydell1-8/+16
The linux-user usage message attempts to line up the columns in its table by calculating the maximum width of any item in them. However for the 'Argument' column it was only accounting for the length of the option switch (eg "-d"), not the additional example text (eg "item[,...]"). This currently has no adverse effects because the widest item in the column happens to be the argumentless "-singlestep" option, but improving the "-d" option help to read "-d item[,...]" exceeds that limit. Fix this by correctly calculating maxarglen as the width of the first column text including a possible option argument, and adjusting its uses to match. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
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