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2025-03-11hw/xen/hvm: Fix Aarch64 typoPhilippe Mathieu-Daudé1-1/+1
There is no TARGET_ARM_64 definition. Luckily enough, when TARGET_AARCH64 is defined, TARGET_ARM also is. Fixes: 733766cd373 ("hw/arm: introduce xenpvh machine") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250305153929.43687-2-philmd@linaro.org>
2025-03-11hw/sd/sdhci: Set reset value of interrupt registersBALATON Zoltan1-0/+1
The interrupt enable registers are not reset to 0 on Freescale eSDHC but some bits are enabled on reset. At least some U-Boot versions seem to expect this and not initialise these registers before expecting interrupts. Use existing vendor property for Freescale eSDHC and set the reset value of the interrupt registers to match Freescale documentation. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-ID: <20250210160329.DDA7F4E600E@zero.eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-03-11system: Declare qemu_[min/max]rampagesize() in 'system/hostmem.h'Philippe Mathieu-Daudé2-3/+3
Both qemu_minrampagesize() and qemu_maxrampagesize() are related to host memory backends, having the following call stack: qemu_minrampagesize() -> find_min_backend_pagesize() -> object_dynamic_cast(obj, TYPE_MEMORY_BACKEND) qemu_maxrampagesize() -> find_max_backend_pagesize() -> object_dynamic_cast(obj, TYPE_MEMORY_BACKEND) Having TYPE_MEMORY_BACKEND defined in "system/hostmem.h": include/system/hostmem.h:23:#define TYPE_MEMORY_BACKEND "memory-backend" Move their prototype declaration to "system/hostmem.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-Id: <20250308230917.18907-7-philmd@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250311085743.21724-2-philmd@linaro.org Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-11block: Remove unused blk_op_is_blocked()Kevin Wolf1-1/+0
Commit fc4e394b28 removed the last caller of blk_op_is_blocked(). Remove the now unused function. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-ID: <20250206165331.379033-1-kwolf@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2025-03-11spapr: Generate random HASHPKEYR for spapr machinesNicholas Piggin1-0/+1
The hypervisor is expected to create a value for the HASHPKEY SPR for each partition. Currently it uses zero for all partitions, use a random number instead, which in theory might make kernel ROP protection more secure. Signed-of-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241219034035.1826173-4-npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11spapr: nested: Add support for reporting Hostwide state counterVaibhav Jain1-6/+61
Add support for reporting Hostwide state counters for nested KVM pseries guests running with 'cap-nested-papr' on Qemu-TCG acting as L0-hypervisor. The Hostwide state counters are statistics about state that L0-hypervisor maintains for the L2-guests and represent the state of all L2-guests, not just a specific one. These stats counters are exposed to L1-Hypervisor by the L0-Hypervisor via a new bit-flag named 'getHostWideState' for the H_GUEST_GET_STATE hcall which is documented at [1]. Once this flag is set the hcall should populate the Guest-State-Elements in the requested GSB with the stat counter values. Currently following five counters are supported: * l0_guest_heap_size_inuse * l0_guest_heap_size_max * l0_guest_pagetable_size_inuse * l0_guest_pagetable_size_max * l0_guest_pagetable_reclaimed At the moment '0' is being reported for all these counters as these counters doesn't align with how L0-Qemu manages Guest memory. The patch implements support for these counters by adding new members to the 'struct SpaprMachineStateNested'. These new members are then plugged into the existing 'guest_state_element_types[]' with the help of a new macro 'GSBE_NESTED_MACHINE_DW' together with a new helper 'get_machine_ptr()'. guest_state_request_check() is updated to ensure correctness of the requested GSB and finally h_guest_getset_state() is updated to handle the newly introduced flag 'GUEST_STATE_REQUEST_HOST_WIDE'. This patch is tested with the proposed linux-kernel implementation to expose these stat-counter as perf-events at [2]. [1] https://lore.kernel.org/all/20241222140247.174998-2-vaibhav@linux.ibm.com [2] https://lore.kernel.org/all/20241222140247.174998-1-vaibhav@linux.ibm.com Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-ID: <20250221155449.530645-1-vaibhav@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc: spapr: Enable 2nd DAWR on Power10 pSeries machineShivaprasad G Bhat1-1/+5
As per the PAPR, bit 0 of byte 64 in pa-features property indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to find whether kvm supports 2nd DAWR or not. If it's supported, allow user to set the pa-feature bit in guest DT using cap-dawr1 machine capability. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Message-ID: <173708681866.1678.11128625982438367069.stgit@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11hw/ssi/pnv_spi: Put a limit to RDR match failuresChalapathi V1-0/+1
There is a possibility that SPI controller can get into loop due to indefinite RDR match failures. Hence put a limit to failures and stop the sequencer. Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20250303141328.23991-5-chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11hw/ssi/pnv_spi: Make bus names distinct for each controllers of a socketChalapathi V1-1/+2
Create a spi buses with distinct names on each socket so that responders are attached to correct SPI controllers. Change the bus name to chipX.spi.<busnum> where X = 0..<num_sockets> QOM tree on a 2 socket machine: (qemu) info qom-tree /machine (powernv10-machine) /chip[0] (power10_v2.0-pnv-chip) /pib_spic[0] (pnv-spi) /chip0.spi.0 (SSI) /xscom-spi[0] (memory-region) /chip[1] (power10_v2.0-pnv-chip) /pib_spic[0] (pnv-spi) /chip1.spi.0 (SSI) /xscom-spi[0] (memory-region) Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Message-ID: <20250303141328.23991-4-chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11hw/ssi/pnv_spi: Replace PnvXferBuffer with Fifo8 structureChalapathi V1-0/+3
In PnvXferBuffer dynamically allocating and freeing is a process overhead. Hence used an existing Fifo8 buffer with capacity of 16 bytes. Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Message-ID: <20250303141328.23991-2-chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/xive2: Check crowd backlog when scanning group backlogFrederic Barrat1-0/+4
When processing a backlog scan for group interrupts, also take into account crowd interrupts. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/xive2: Support crowd-matching when looking for targetFrederic Barrat2-6/+7
XIVE crowd sizes are encoded into a 2-bit field as follows: 0: 0b00 2: 0b01 4: 0b10 16: 0b11 A crowd size of 8 is not supported. If an END is defined with the 'crowd' bit set, then a target can be running on different blocks. It means that some bits from the block VP are masked when looking for a match. It is similar to groups, but on the block instead of the VP index. Most of the changes are due to passing the extra argument 'crowd' all the way to the function checking for matches. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/xive2: Add support for MMIO operations on the NVPG/NVC BARFrederic Barrat2-0/+12
Add support for the NVPG and NVC BARs. Access to the BAR pages will cause backlog counter operations to either increment or decriment the counter. Also added qtests for the same. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/xive2: Process group backlog when updating the CPPRFrederic Barrat1-0/+4
When the hypervisor or OS pushes a new value to the CPPR, if the LSMFB value is lower than the new CPPR value, there could be a pending group interrupt in the backlog, so it needs to be scanned. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/xive2: Add undelivered group interrupt to backlogFrederic Barrat2-0/+6
When a group interrupt cannot be delivered, we need to: - increment the backlog counter for the group in the NVG table (if the END is configured to keep a backlog). - start a broadcast operation to set the LSMFB field on matching CPUs which can't take the interrupt now because they're running at too high a priority. [npiggin: squash in fixes from milesg] [milesg: only load the NVP if the END is !ignore] [milesg: always broadcast backlog, not only when there are precluded VPs] Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/xive2: Support group-matching when looking for targetFrederic Barrat2-5/+7
If an END has the 'i' bit set (ignore), then it targets a group of VPs. The size of the group depends on the VP index of the target (first 0 found when looking at the least significant bits of the index) so a mask is applied on the VP index of a running thread to know if we have a match. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/xive2: Add grouping level to notificationFrederic Barrat2-7/+27
The NSR has a (so far unused) grouping level field. When a interrupt is presented, that field tells the hypervisor or OS if the interrupt is for an individual VP or for a VP-group/crowd. This patch reworks the presentation API to allow to set/unset the level when raising/accepting an interrupt. It also renames xive_tctx_ipb_update() to xive_tctx_pipr_update() as the IPB is only used for VP-specific target, whereas the PIPR always needs to be updated. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/xive: Rename ipb_to_pipr() to xive_ipb_to_pipr()Michael Kowal1-4/+12
Rename to follow the convention of the other function names. Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/xive2: Update NVP save/restore for group attributesFrederic Barrat1-3/+7
If the 'H' attribute is set on the NVP structure, the hardware automatically saves and restores some attributes from the TIMA in the NVP structure. The group-specific attributes LSMFB, LGS and T have an extra flag to individually control what is saved/restored. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/pnv: Move PNOR to offset 0 in the ISA FW spaceNicholas Piggin1-2/+4
skiboot has a bug that does not handle ISA FW access correctly for IDSEL devices > 0, and the current PNOR default address and size puts 64MB in device 0 and 64MB in device 1, which causes skiboot to hit this bug and breaks PNOR accesses. Move the PNOR address down to 0 for now, so a 256MB PNOR can be accessed via device 0. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/pnv/occ: Implement a basic dynamic OCC modelNicholas Piggin1-0/+3
The OCC is an On Chip Controller that handles various thermal and power management. It is a PPC405 microcontroller that runs its own firmware which is out of scope of the powernv machine model. Some dynamic behaviour and interfaces that are important for host CPU testing can be implemented with a much simpler state machine. This change adds a 100ms timer that ticks through a simple state machine that looks for "OCC command requests" coming from host firmware, and responds to them. For now the powercap command is implemented because that is used by OPAL and exported to Linux and is easy to test. $ F=/sys/firmware/opal/powercap/system-powercap/powercap-current $ cat $F 100 $ echo 50 | sudo tee $F 50 $ cat $F 50 Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/pnv: Make HOMER memory a RAM regionNicholas Piggin2-4/+7
The HOMER is a region of memory used by host and firmware and microconrollers. It has very little logic by itself, just some BAR registers. Users of this memory should operate on it rather than have HOMER implement them with MMIO registers, which is not the right model. This change switches the implementation of HOMER from MMIO to RAM, and moves the OCC register implementation to in-memory structure accesses performed by the OCC model. This has the downside that access to unimplemented regions of HOMER are no longer flagged. Perhaps that could be done by adding a memory region for HOMER, and ram subregions under that for each implemented part. But for now this takes the simpler approach. Note: This brings some data structure definitions from skiboot, which does not match QEMU coding style but is not changed to make comparisons and updates simpler. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/pnv/homer: class-based base and sizeNicholas Piggin2-5/+8
Put HOMER memory region base and size into the class, to allow more code-reuse between different machines in later changes. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11ppc/pnv/phb4: Add pervasive chiplet support to PHB4/5Nicholas Piggin2-0/+9
Each non-core chiplet on a chip has a "pervasive chiplet" unit and its xscom register set. This adds support for PHB4/5. skiboot reads the CPLT_CONF1 register in __phb4/5_get_max_link_width(), which shows up as unimplemented xscom reads. Set a value in PCI CONF1 register's link-width field to demonstrate skiboot doing something interesting with it. In the bigger picture, it might be better to model the pervasive chiplet type as parent that each non-core chiplet model derives from. For now this is enough to get the PHB registers implemented and working for skiboot, and provides a second example (after the N1 chiplet) that will help if the design is reworked as such. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-11Merge tag 'migration-20250310-pull-request' of ↵Stefan Hajnoczi2-0/+4
https://gitlab.com/farosas/qemu into staging Migration pull request - Fix use-after-free in incoming migration - Improve cpr migration blocker for volatile ram - Fix RDMA migration # -----BEGIN PGP SIGNATURE----- # # iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmfPaCAQHGZhcm9zYXNA # c3VzZS5kZQAKCRDHmNx0G+wxnQy9EADRp/6GaSzoqWgafU8DGM5Q69HyKiZ888DZ # 7qXqJeH3c95nvOnIw2BMhUYX4t8kkAbUcWlr7L8KCjZT/6N/d1/Z5fimqymRkw4x # +8kDyADv5FY0339aMLf3qBbIAQj/gvPvg8H+e+hXfokZqoYgLXZ0eqNAz8MjIcyN # +A+waEBMLNvTgZyTQl2TbCvb+mbRial8u8C9BIoILhn/gNuoMX7lbt0tq41HZwe0 # l3v16jnXlsDvQUXp99bGySomRgkcYqdAt+HWHLje3frT/Ap8dGaUJKlpgJ8DXJiA # fV1reKihJdj37q9GSG8cR02W+ATBesiecufV4TUPNQYQzTdxn3fOMwdc3Pck074D # YAQxFT20OPou+NRxjYoHT/GqFUY36/2qBJpt7TY3ramdklHJhXpRyedK4rppTZNn # pC3lnbpA/LHRmfD1Nh0CRmqZpbV+qW1BWEgMwk4qui46BxYWHxKHFpxAuwlJQmcw # RxY8qPhIXQM03tiTgIddBNDZLoVqRoUP7YpzR7MMa1rz0T5inNFMcNGm72WpKODE # rzpw4ezXO7+D4/QmMq3PoPfhFv3QFnH6jaGj8JkJM378KLvh4fQ0woXtDKFl4Tbq # 1oBZ17WUv6aHr75b+KMyKJNLinvMu5WF5WoRYIt1lNXaqk7I494yvIjtRrimWZIS # Z5Q0tpUmpw== # =yEH0 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 11 Mar 2025 06:30:56 HKT # gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D # gpg: issuer "farosas@suse.de" # gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown] # gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D * tag 'migration-20250310-pull-request' of https://gitlab.com/farosas/qemu: migration: Prioritize RDMA in ram_save_target_page() migration: ram block cpr blockers migration: Fix UAF for incoming migration on MigrationState Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-11Merge tag 'pull-xen-20250310' of ↵Stefan Hajnoczi1-0/+4
https://xenbits.xen.org/git-http/people/aperard/qemu-dm into staging Xen queue: * xen/passthrough: use gsi to map pirq when dom0 is PVH * Fix missing xenstore node from xen-block backend * Fix xen mapcache extraneous invalidate # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEE+AwAYwjiLP2KkueYDPVXL9f7Va8FAmfO+nEACgkQDPVXL9f7 # Va+QYggA9dmxMGDO05UEd2ZPv/Goub37Le44qBN4oeXizVRZgGUs2w9ETBXhPZus # 34aI8CTID4fcH4rgF4LgJ4XuyOxYwP1ot8EpDHQg+ji2nyHeMpAyePTfubprq17U # APN6Qqefd9X+TX+W9zUS5jV/AXO+apGX+tmVkVexFuy4gSRGSVCPoibHePtoLH9G # 3rSREjdEx7ByY6ieCV5x3zHPp5tmnLWeHpNCVc5x6NplBslQduBz6vOqLNWB1LKO # 3a/lYcvTn9PIla1zpvGNbeTsPv2lcdx3SccThcZmyTv2PDm1kzyUOIo1lSIP6bb3 # LjCl3dm1mfxAGEaZ+//rsRhTH8d5ew== # =K79y # -----END PGP SIGNATURE----- # gpg: Signature made Mon 10 Mar 2025 22:42:57 HKT # gpg: using RSA key F80C006308E22CFD8A92E7980CF5572FD7FB55AF # gpg: Good signature from "Anthony PERARD <anthony.perard@gmail.com>" [unknown] # gpg: aka "Anthony PERARD <anthony.perard@vates.tech>" [unknown] # gpg: aka "Anthony PERARD <anthony@xenproject.org>" [unknown] # gpg: aka "Anthony PERARD <anthony.perard@citrix.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 5379 2F71 024C 600F 778A 7161 D8D5 7199 DF83 42C8 # Subkey fingerprint: F80C 0063 08E2 2CFD 8A92 E798 0CF5 572F D7FB 55AF * tag 'pull-xen-20250310' of https://xenbits.xen.org/git-http/people/aperard/qemu-dm: xen: No need to flush the mapcache for grants hw/xen: Add "mode" parameter to xen-block devices xen/passthrough: use gsi to map pirq when dom0 is PVH Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-11Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into stagingStefan Hajnoczi1-2/+3
# -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEIV1G9IJGaJ7HfzVi7wSWWzmNYhEFAmfO1zkACgkQ7wSWWzmN # YhET+wf+PkaGeFTNUrOtWpl35fSMKlmOVbb1fkPfuhVBmeY2Vh1EIN3OjqnzdV0F # wxpuk+wwmFiuV1n6RNuMHQ0nz1mhgsSlZh93N5rArC/PUr3iViaT0cb82RjwxhaI # RODBhhy7V9WxEhT9hR8sCP2ky2mrKgcYbjiIEw+IvFZOVQa58rMr2h/cbAb/iH4l # 7T9Wba03JBqOS6qgzSFZOMxvqnYdVjhqXN8M6W9ngRJOjPEAkTB6Evwep6anRjcM # mCUOgkf2sgQwKve8pYAeTMkzXFctvTc/qCU4ZbN8XcoKVVxe2jllGQqdOpMskPEf # slOuINeW5M0K5gyjsb/huqcOTfDI2A== # =/Y0+ # -----END PGP SIGNATURE----- # gpg: Signature made Mon 10 Mar 2025 20:12:41 HKT # gpg: using RSA key 215D46F48246689EC77F3562EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [full] # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * tag 'net-pull-request' of https://github.com/jasowang/qemu: tap-linux: Open ipvtap and macvtap Revert "hw/net/net_tx_pkt: Fix overrun in update_sctp_checksum()" util/iov: Do not assert offset is in iov net: move backend cleanup to NIC cleanup net: parameterize the removing client from nc list Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-10migration: ram block cpr blockersSteve Sistare2-0/+4
Unlike cpr-reboot mode, cpr-transfer mode cannot save volatile ram blocks in the migration stream file and recreate them later, because the physical memory for the blocks is pinned and registered for vfio. Add a blocker for volatile ram blocks. Also add a blocker for RAM_GUEST_MEMFD. Preserving guest_memfd may be sufficient for CPR, but it has not been tested yet. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-ID: <1740667681-257312-1-git-send-email-steven.sistare@oracle.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-03-10xen/passthrough: use gsi to map pirq when dom0 is PVHJiqian Chen1-0/+4
In PVH dom0, when passthrough a device to domU, QEMU code xen_pt_realize->xc_physdev_map_pirq wants to use gsi, but in current codes the gsi number is got from file /sys/bus/pci/devices/<sbdf>/irq, that is wrong, because irq is not equal with gsi, they are in different spaces, so pirq mapping fails. To solve above problem, use new interface of Xen, xc_pcidev_get_gsi to get gsi and use xc_physdev_map_pirq_gsi to map pirq when dom0 is PVH. Signed-off-by: Jiqian Chen <Jiqian.Chen@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Jiqian Chen <Jiqian.Chen@amd.com> Acked-by: Anthony PERARD <anthony@xenproject.org> Reviewed-by: Stewart Hildebrand <stewart.hildebrand@amd.com> Message-Id: <20241106061418.3655304-1-Jiqian.Chen@amd.com> Signed-off-by: Anthony PERARD <anthony.perard@vates.tech>
2025-03-10include/qemu: plugin-memory.h doesn't need cpu-defs.hAlex Bennée1-1/+0
hwaddr is a fixed size on all builds. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250304222439.2035603-23-alex.bennee@linaro.org>
2025-03-10util/iov: Do not assert offset is in iovAkihiko Odaki1-2/+3
iov_from_buf(), iov_to_buf(), iov_memset(), and iov_copy() asserts that the given offset fits in the iov while tolerating the specified number of bytes to operate with to be greater than the size of iov. This is inconsistent so remove the assertions. Asserting the offset fits in the iov makes sense if it is expected that there are other operations that process the content before the offset and the content is processed in order. Under this expectation, the offset should point to the end of bytes that are previously processed and fit in the iov. However, this expectation depends on the details of the caller, and did not hold true at least one case and required code to check iov_size(), which is added with commit 83ddb3dbba2e ("hw/net/net_tx_pkt: Fix overrun in update_sctp_checksum()"). Adding such a check is inefficient and error-prone. These functions already tolerate the specified number of bytes to operate with to be greater than the size of iov to avoid such checks so remove the assertions to tolerate invalid offset as well. They return the number of bytes they operated with so their callers can still check the returned value to ensure there are sufficient space at the given offset. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2025-03-10Merge tag 'accel-cpus-20250309' of https://github.com/philmd/qemu into stagingStefan Hajnoczi4-22/+51
Generic CPUs / accelerators patch queue - Reduce "exec/tb-flush.h" inclusion on linux-user - Consider alignment in bsd-user's mmap_find_vma() - Unify MMAP common user emulation API - Simplify cpu-target.c further - Prefer cached CpuClass over CPU_GET_CLASS() macro - Restrict CPU has_work() handlers to system emulation - Consolidate core exec/vCPU section in MAINTAINERS # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmfN1NgACgkQ4+MsLN6t # wN6BghAAr5WBteo7OiNRyTA0Ilg+nOcTf6Re08CgWf/3TIMljEPq8o/tLQOxiFke # AMktDlvYTyg4BWa5UdAKLpj7N7eyHcXrqv95A6Lg/xoGdlbqfYIpyX7/5h0pV70f # z8WUj2/YMpoyXxvvAjw4YtUqHIWZhSTIBsFqJ6jALl6T7fouo8y++AWn/L+zY4tO # /qqC6djJwufphPJWm2NvG+nvf+T60C+4JUc8CkjYQsyL3K3HpoAgzrgb/6VRtHob # nKfORPboKEVSE1Z52GnmM9eMsZjbWOz9bkEN69yfRbHHQNuvsicok+V59PnWWDYd # JX6cC5ukJUJlgYDKOj2jCg9OouoV4mRYRqYYWPtE8WkGLoeJu4mV1AEkVB7h3lTA # BtUu4ohsrk/krfyB89apu8SqDPya6F4TDqJpGmAqlAG2UWJwrECuJV82uTDZql0R # MqnCUYb7OQBkdb9CoqFi47jTYlqgdVLKekS8udXLCaqWggki8Nb1GVQ09LFyv3NF # JlQVNNQG3D2V7JIDd2aXgr4PmhmV2oPv+HYxW+SPxU2qDHIU93krkKyi0TRk0mSC # sWvJYBJcwbXlnMD5clad1bTLZrK5Csl5WkX8I0d0feqeRPSXC2YBTwL2/GgzT8qF # n/2dxB3Lf+1LUl6KAv3kT9lONtqic0J9oBBcPUjVog2ikAD7+Vo= # =TZua # -----END PGP SIGNATURE----- # gpg: Signature made Mon 10 Mar 2025 01:50:16 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'accel-cpus-20250309' of https://github.com/philmd/qemu: (38 commits) MAINTAINERS: Consolidate core exec/vCPU handling section cpus: Remove CPUClass::has_work() handler target/xtensa: Move has_work() from CPUClass to SysemuCPUOps target/tricore: Move has_work() from CPUClass to SysemuCPUOps target/sparc: Move has_work() from CPUClass to SysemuCPUOps target/sh4: Move has_work() from CPUClass to SysemuCPUOps target/s390x: Move has_work() from CPUClass to SysemuCPUOps target/s390x: Restrict I/O handler installers to system emulation target/rx: Move has_work() from CPUClass to SysemuCPUOps target/riscv: Move has_work() from CPUClass to SysemuCPUOps target/ppc: Move has_work() from CPUClass to SysemuCPUOps target/openrisc: Move has_work() from CPUClass to SysemuCPUOps target/mips: Move has_work() from CPUClass to SysemuCPUOps target/microblaze: Move has_work() from CPUClass to SysemuCPUOps target/m68k: Move has_work() from CPUClass to SysemuCPUOps target/loongarch: Move has_work() from CPUClass to SysemuCPUOps target/i386: Move has_work() from CPUClass to SysemuCPUOps target/hppa: Move has_work() from CPUClass to SysemuCPUOps target/hexagon: Remove CPUClass:has_work() handler target/avr: Move has_work() from CPUClass to SysemuCPUOps ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-09cpus: Remove CPUClass::has_work() handlerPhilippe Mathieu-Daudé2-3/+2
All handlers have been converted to SysemuCPUOps::has_work(). Remove CPUClass::has_work along with cpu_common_has_work() and simplify cpu_has_work(), making SysemuCPUOps::has_work handler mandatory. Note, since cpu-common.c is in meson's common_ss[] source set, we must define cpu_exec_class_post_init() in cpu-target.c (which is in the specific_ss[] source set) to have CONFIG_USER_ONLY defined. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250125170125.32855-25-philmd@linaro.org>
2025-03-09cpus: Introduce SysemuCPUOps::has_work() handlerPhilippe Mathieu-Daudé2-1/+5
SysemuCPUOps::has_work() is similar to CPUClass::has_work(), but only exposed on system emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250125170125.32855-4-philmd@linaro.org>
2025-03-09cpus: Un-inline cpu_has_work()Philippe Mathieu-Daudé1-5/+1
In order to expand cpu_has_work(), un-inline it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250125170125.32855-3-philmd@linaro.org>
2025-03-09cpus: Restrict cpu_has_work() to system emulationPhilippe Mathieu-Daudé1-14/+14
This method is not used on user emulation, because there is always work to do there. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250125170125.32855-2-philmd@linaro.org>
2025-03-09cpus: Prefer cached CpuClass over CPU_GET_CLASS() macroPhilippe Mathieu-Daudé1-7/+3
CpuState caches its CPUClass since commit 6fbdff87062 ("cpu: cache CPUClass in CPUState for hot code paths"), use it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250122093028.52416-5-philmd@linaro.org>
2025-03-09cpus: Register VMState per user / system emulationPhilippe Mathieu-Daudé1-0/+2
Simplify cpu-target.c by extracting mixed vmstate code into the cpu_vmstate_register() / cpu_vmstate_unregister() helpers, implemented in cpu-user.c and cpu-system.c. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-20-philmd@linaro.org>
2025-03-09user: Extract common MMAP API to 'user/mmap.h'Philippe Mathieu-Daudé1-0/+32
Keep common MMAP-related declarations in a single place. Note, this disable ThreadSafetyAnalysis on Linux for: - mmap_fork_start() - mmap_fork_end(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250308122842.76377-4-philmd@linaro.org>
2025-03-09hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1Jamin Lin1-0/+1
The design of INTC controllers has significantly changed in AST2700 A1. There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the limitation of interrupt numbers of processors, the interrupts are merged every 32 sources for interrupt numbers greater than 127. There are two levels of interrupt controllers, INTC(CPUD Die) and INTCIO (IO Die). The interrupt sources of INTC are the interrupt numbers from INTC_0 to INTC_127 and interrupts from INTCIO. The interrupt sources of INTCIO are the interrupt numbers greater than INTC_127. INTC_IO controls the interrupts INTC_128 to INTC_319 only. Currently, only GIC 192 to 201 are supported, and their source interrupts are from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for GIC 192-201. The design of the orgates for GICINT 196 is as follows: It has interrupt sources ranging from 0 to 31, with its output pin connected to INTCIO "T0 GICINT_196". The output pin is then connected to INTC "GIC_192_201" at bit 4, and its bit 4 output should be connected to GIC 196. The design of INTC GIC_192_201 have 10 output pins, mapped as following: Bit 0 -> GIC 192 Bit 1 -> GIC 193 Bit 2 -> GIC 194 Bit 3 -> GIC 195 Bit 4 -> GIC 196 To support both AST2700 A1 and A0, INTC input pins 1 to 9 and output pins 10 to 18 remain to support GIC 128-136, which source interrupts from INTC. These will be removed if we decide not to support AST2700 A0 in the future. |-------------------------------------------------------------------------------------------------------| | AST2700 A1 Design | | To GICINT196 | | | | ETH1 |-----------| |--------------------------| |--------------| | | -------->|0 | | INTCIO | | orgates[0] | | | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | | | -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | | | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | | | -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| | | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | | | -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | | | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | | | -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | | | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | | | -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | | | UART3 | 26| |--------------------------| |--------------| | | | ---------|10 27| | | | UART5 | 28| | | | -------->|11 29| | | | UART6 | | | | | -------->|12 30| |-----------------------------------------------------------------------| | | UART7 | 31| | | | -------->|13 | | | | UART8 | OR[0:31] | | |------------------------------| |----------| | | -------->|14 | | | INTC | | GIC | | | UART9 | | | |inpin[0:0]--------->outpin[0] |---------->|192 | | | -------->|15 | | |inpin[0:1]--------->outpin[1] |---------->|193 | | | UART10 | | | |inpin[0:2]--------->outpin[2] |---------->|194 | | | -------->|16 | | |inpin[0:3]--------->outpin[3] |---------->|195 | | | UART11 | | |--------------> |inpin[0:4]--------->outpin[4] |---------->|196 | | | -------->|17 | |inpin[0:5]--------->outpin[5] |---------->|197 | | | UART12 | | |inpin[0:6]--------->outpin[6] |---------->|198 | | | -------->|18 | |inpin[0:7]--------->outpin[7] |---------->|199 | | | |-----------| |inpin[0:8]--------->outpin[8] |---------->|200 | | | |inpin[0:9]--------->outpin[9] |---------->|201 | | |-------------------------------------------------------------------------------------------------------| |-------------------------------------------------------------------------------------------------------| | ETH1 |-----------| orgates[1]------->|inpin[1]----------->outpin[10]|---------->|128 | | | -------->|0 | orgates[2]------->|inpin[2]----------->outpin[11]|---------->|129 | | | ETH2 | 4| orgates[3]------->|inpin[3]----------->outpin[12]|---------->|130 | | | -------->|1 5| orgates[4]------->|inpin[4]----------->outpin[13]|---------->|131 | | | ETH3 | 6|---->orgates[5]------->|inpin[5]----------->outpin[14]|---------->|132 | | | -------->|2 19| orgates[6]------->|inpin[6]----------->outpin[15]|---------->|133 | | | UART0 | 20| orgates[7]------->|inpin[7]----------->outpin[16]|---------->|134 | | | -------->|7 21| orgates[8]------->|inpin[8]----------->outpin[17]|---------->|135 | | | UART1 | 22| orgates[9]------->|inpin[9]----------->outpin[18]|---------->|136 | | | -------->|8 23| |------------------------------| |----------| | | UART2 | 24| | | -------->|9 25| AST2700 A0 Design | | UART3 | 26| | | -------->|10 27| | | UART5 | 28| | | -------->|11 29| GICINT132 | | UART6 | | | | -------->|12 30| | | UART7 | 31| | | -------->|13 | | | UART8 | OR[0:31] | | | -------->|14 | | | UART9 | | | | -------->|15 | | | UART10 | | | | -------->|16 | | | UART11 | | | | -------->|17 | | | UART12 | | | | -------->|18 | | | |-----------| | | | |-------------------------------------------------------------------------------------------------------| Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-22-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two InstancesJamin Lin1-1/+1
Updated Aspeed27x0SoCState to include an intc[2] array instead of a single AspeedINTCState instance. Modified aspeed_soc_ast2700_get_irq and aspeed_soc_ast2700_get_irq_index to correctly reference the corresponding interrupt controller instance and OR gate index. Currently, only GIC 192 to 201 are supported, and their source interrupts are from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for GIC 192-201. To support both AST2700 A1 and A0, INTC input pins 1 to 9 and output pins 10 to 18 remain to support GIC 128-136, which source interrupts from INTC. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-21-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon RevisionsJamin Lin1-0/+2
Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV to identify the A1 silicon revisions. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-19-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09hw/intc/aspeed: Add Support for AST2700 INTCIO ControllerJamin Lin1-0/+1
Introduce a new ast2700 INTCIO class to support AST2700 INTCIO. Added new register definitions for INTCIO, including enable and status registers for IRQs GICINT192 through GICINT197. Created a dedicated IRQ array for INTCIO, supporting six input pins and six output pins, aligning with the newly defined registers. Implemented "aspeed_intcio_read" and "aspeed_intcio_write" to handle INTCIO-specific register access. To GICINT196 | ETH1 |-----------| |--------------------------| -------->|0 | | INTCIO | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]| -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]| ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]| -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]| UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]| -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]| UART1 | 22| |--------------------------| -------->|8 23| UART2 | 24| -------->|9 25| UART3 | 26| ---------|10 27| UART5 | 28| -------->|11 29| UART6 | | -------->|12 30| UART7 | 31| -------->|13 | UART8 | OR[0:31] | -------->|14 | UART9 | | -------->|15 | UART10 | | -------->|16 | UART11 | | -------->|17 | UART12 | | -------->|18 | |-----------| Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-18-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09hw/intc/aspeed: Add Support for Multi-Output IRQ HandlingJamin Lin1-2/+2
This update introduces support for handling multi-output IRQs in the AST2700 interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps 1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a specific IRQ. Implemented "aspeed_intc_set_irq_handler_multi_outpins" to handle IRQs with multiple output pins. Introduced "aspeed_intc_status_handler_multi_outpins" for managing status registers associated with multi-output IRQs. Added new IRQ definitions for GICINT192_201 in INTC. Adjusted the IRQ array to accommodate 10 input pins and 19 output pins, aligning with the new GICINT192_201 mappings. |------------------------------| | INTC | |inpin[0:0]--------->outpin[0] | |inpin[0:1]--------->outpin[1] | |inpin[0:2]--------->outpin[2] | |inpin[0:3]--------->outpin[3] | orgates[0]-------> |inpin[0:4]--------->outpin[4] | |inpin[0:5]--------->outpin[5] | |inpin[0:6]--------->outpin[6] | |inpin[0:7]--------->outpin[7] | |inpin[0:8]--------->outpin[8] | |inpin[0:9]--------->outpin[9] | | | orgates[1]------> |inpin[1]----------->outpin[10]| orgates[2]------> |inpin[2]----------->outpin[11]| orgates[3]------> |inpin[3]----------->outpin[12]| orgates[4]------> |inpin[4]----------->outpin[13]| orgates[5]------> |inpin[5]----------->outpin[14]| orgates[6]------> |inpin[6]----------->outpin[15]| orgates[7]------> |inpin[7]----------->outpin[16]| orgates[8]------> |inpin[8]----------->outpin[17]| orgates[9]------> |inpin[9]----------->outpin[18]| |------------------------------| Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-17-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and ↵Jamin Lin1-0/+10
register address The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to derive the IRQ index numbers. However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ pin to 10 output IRQ pins. The pin numbers for input and output are different. It is difficult to use a formula to determine the index number of INTC model supported input and output IRQs. To simplify and improve readability, introduces the AspeedINTCIRQ structure to save the input/output IRQ index and its enable/status register address. Introduce the "aspeed_2700_intc_irqs" table to store IRQ information for INTC. Introduce the "aspeed_intc_get_irq" function to retrieve the input/output IRQ pin index from the provided status/enable register address. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-15-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09hw/intc/aspeed: Add support for multiple output pins in INTCJamin Lin1-2/+3
Added support for multiple output pins in the INTC controller to accommodate the AST2700 A1. Introduced "num_outpins" to represent the number of output pins. Updated the IRQ handling logic to initialize and connect output pins separately from input pins. Modified the "aspeed_soc_ast2700_realize" function to connect source orgates to INTC and INTC to GIC128 - GIC136. Updated the "aspeed_intc_realize" function to initialize output pins. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-13-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09hw/intc/aspeed: Rename num_ints to num_inpins for clarityJamin Lin1-5/+6
To support AST2700 A1, some registers of the INTC(CPU Die) support one input pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC controller code for better clarity and consistency in naming conventions. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-12-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09hw/intc/aspeed: Support different memory region opsJamin Lin1-0/+1
The previous implementation set the "aspeed_intc_ops" struct, containing read and write callbacks, to be used when I/O is performed on the INTC region. Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used for INTC (CPU Die). To support the INTCIO (IO Die) model, introduces a new "reg_ops" class attribute. This allows setting different memory region operations to support different INTC models. Will introduce "aspeed_intcio_read" and "aspeed_intcio_write" callback functions are used for INTCIO. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-11-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09hw/intc/aspeed: Reduce regs array size by adding a register sub-regionJamin Lin1-0/+1
Currently, the size of the "regs" array is 0x2000, which is too large. So far, it only uses "GICINT128 to `GICINT134", and the offsets from 0 to 0x1000 are unused. To save code size and avoid mapping large unused gaps, update to only map the useful set of registers: INTC register [0x1000 – 0x1804] Update "reg_size" to 0x808. Introduce a new class attribute "reg_offset" to set the start offset of a "INTC" sub-region. Set the "reg_offset" to 0x1000 for INTC registers. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-6-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09hw/intc/aspeed: Support setting different register sizeJamin Lin1-1/+1
Currently, the size of the regs array is 0x2000, which is too large. So far, it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000 are unused. To save code size, introduce a new class attribute "reg_size" to set the different register sizes for the INTC models in AST2700 and add a regs sub-region in the memory container. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
generated by cgit v1.1 at 2025-09-23 02:25:22 +0000