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2021-09-29ppc/xive: Export priority_to_ipb() helperCédric Le Goater1-0/+11
2021-09-29host-utils: introduce uabs64()Luis Pires1-0/+8
2021-09-29host-utils: fix missing zero-extension in divs128Luis Pires1-1/+1
2021-09-27hw/loader: Restrict PC_ROM_* definitions to hw/i386/pcPhilippe Mathieu-Daudé1-6/+0
2021-09-24Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20210921' into stagingRichard Henderson2-1/+15
2021-09-24hw/nvme: fix verification of select field in namespace attachmentNaveen Nagar1-0/+5
2021-09-21hw/core: Make do_unaligned_access noreturnRichard Henderson1-1/+2
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson1-0/+13
2021-09-21Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...Richard Henderson8-61/+165
2021-09-21Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210921'...Peter Maydell1-1/+11
2021-09-21arm/hvf: Add a WFI handlerPeter Collingbourne1-0/+1
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel1-0/+2
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel1-18/+36
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel1-0/+0
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis1-1/+13
2021-09-21hw/timer: Add SiFive PWM supportAlistair Francis1-0/+62
2021-09-21hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis1-0/+2
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis1-0/+4
2021-09-21hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis1-0/+2
2021-09-21hw/intc: sifive_clint: Use RISC-V CPU GPIO linesAlistair Francis1-0/+2
2021-09-20hvf: Add Apple Silicon supportAlexander Graf1-1/+9
2021-09-20hvf: Introduce hvf_arch_init() callbackAlexander Graf1-0/+1
2021-09-20hw/arm/aspeed: Allow machine to set UART defaultPeter Delevoryas2-0/+2
2021-09-20aspeed: Emulate the AST2600A3Joel Stanley1-0/+2
2021-09-20watchdog: aspeed: Sanitize control register valuesAndrew Jeffery1-0/+1
2021-09-16Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.2-pul...Peter Maydell1-0/+4
2021-09-16Merge remote-tracking branch 'remotes/kraxel/tags/vga-20210916-pull-request' ...Peter Maydell3-2/+9
2021-09-15block: Clarify that @bytes is no limit on *pnumHanna Reitz1-0/+9
2021-09-15block: block-status cache for data regionsHanna Reitz1-0/+50
2021-09-15block: Drop BDS comment regarding bdrv_append()Hanna Reitz1-6/+0
2021-09-15qdev: Complete qdev_init_gpio_out() documentationPhilippe Mathieu-Daudé1-0/+4
2021-09-15Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210914-4' in...Peter Maydell4-30/+43
2021-09-15ui/gtk-egl: Wait for the draw signal for dmabuf blobsVivek Kasireddy1-0/+2
2021-09-15ui: Create sync objects and fences only for blobsVivek Kasireddy3-0/+3
2021-09-15ui/egl: Add egl helpers to help with synchronizationVivek Kasireddy2-0/+4
2021-09-15ui/gtk: Create a common release_dmabuf helperVivek Kasireddy1-2/+0
2021-09-14accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemuPhilippe Mathieu-Daudé1-2/+2
2021-09-14accel/tcg: Rename user-mode do_interrupt hack as fake_user_interruptPhilippe Mathieu-Daudé1-8/+14
2021-09-14tcg: Remove tcg_global_reg_new definesBin Meng1-2/+0
2021-09-14accel/tcg: Clear PAGE_WRITE before translationIlya Leoshkevich2-16/+24
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich1-4/+5
2021-09-14chardev: add some comments about the class methodsMarc-André Lureau1-0/+33
2021-09-14chardev: remove needless class methodMarc-André Lureau1-1/+0
2021-09-13Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210913-...Peter Maydell4-1/+70
2021-09-13qdev: Support marking individual buses as 'full'Peter Maydell1-0/+24
2021-09-13hw/arm/virt: add ITS support in virt GICShashi Mallela1-0/+2
2021-09-13hw/intc: GICv3 redistributor ITS processingShashi Mallela1-0/+7
2021-09-13hw/intc: GICv3 ITS Feature enablementShashi Mallela1-0/+1
2021-09-13hw/intc: GICv3 ITS Command processingShashi Mallela1-0/+2
2021-09-13hw/intc: GICv3 ITS register definitions addedShashi Mallela2-0/+26
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