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2021-09-05Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell9-15/+12
pc,pci,virtio: fixes, cleanups Fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sat 04 Sep 2021 22:34:10 BST # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (35 commits) vhost-vdpa: remove the unncessary queue_index assignment vhost-vdpa: fix the wrong assertion in vhost_vdpa_init() vhost-vdpa: tweak the error label in vhost_vdpa_add() vhost-vdpa: fix leaking of vhost_net in vhost_vdpa_add() vhost-vdpa: don't cleanup twice in vhost_vdpa_add() vhost-vdpa: remove the unnecessary check in vhost_vdpa_add() vhost_net: do not assume nvqs is always 2 vhost: use unsigned int for nvqs vhost_net: remove the meaningless assignment in vhost_net_start_one() vhost-vdpa: correctly return err in vhost_vdpa_set_backend_cap() vhost-vdpa: remove unused variable "acked_features" tests/vhost-user-bridge.c: Fix typo in help message tests/vhost-user-bridge.c: Sanity check socket path length hw/virtio: Add flatview update in vhost_user_cleanup() hw/virtio: Remove NULL check in virtio_free_region_cache() hw/virtio: Document virtio_queue_packed_empty_rcu is called within RCU MAINTAINERS: Added myself as a reviewer for acpi/smbios subsystem hw/acpi: use existing references to pci device struct within functions hw/pci: remove all references to find_i440fx function hw/i386/acpi-build: Get NUMA information from struct NumaState ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-04vhost_net: do not assume nvqs is always 2Jason Wang1-0/+1
This patch switches to initialize dev.nvqs from the VhostNetOptions instead of assuming it was 2. This is useful for implementing control virtqueue support which will be a single vhost_net structure with a single cvq. Note that nvqs is still set to 2 for all users and this patch does not change functionality. Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Eli Cohen <elic@nvidia.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20210903091031.47303-6-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04vhost: use unsigned int for nvqsJason Wang1-1/+1
Switch to use unsigned int for nvqs since it's not expected to be negative. Reviewed-by: Eli Cohen <elic@nvidia.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20210903091031.47303-5-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04hw/pci: remove all references to find_i440fx functionAni Sinha1-1/+0
commit c0e427d6eb5fefc538 ("hw/acpi/ich9: Enable ACPI PCI hot-plug") removed all uses of find_i440fx() function. This has been replaced by the more generic call acpi_get_i386_pci_host() which maybe able to find the root bus both for i440fx machine type as well as for the q35 machine type. There seems to be no more any need to maintain a i440fx specific version of the api call. Remove it. Tested by building from a clean tree successfully. Signed-off-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210825031949.919376-2-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04hw/i386/acpi-build: Get NUMA information from struct NumaStateJingqi Liu1-4/+0
Since commits aa57020774b ("numa: move numa global variable nb_numa_nodes into MachineState") and 7e721e7b10e ("numa: move numa global variable numa_info into MachineState"), we can get NUMA information completely from MachineState::numa_state. Remove PCMachineState::numa_nodes and PCMachineState::node_mem, since they are just copied from MachineState::numa_state. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Jingqi Liu <jingqi.liu@intel.com> Message-Id: <20210823011254.28506-1-jingqi.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04virtio-bus: introduce iommu_enabled()Jason Wang1-1/+3
This patch introduce a new method for the virtio-bus for the transport to report whether or not the IOMMU is enabled for the device. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20210804034803.1644-2-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04acpi: Delete broken ACPI_GED_X86 macroEduardo Habkost1-2/+0
The macro never worked and never will, because the AcpiGedX86State type never existed. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20210805193431.307761-2-ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04hw/virtio: move vhost_set_backend_type() to vhost.cTiberiu Georgescu2-6/+4
Just a small refactor patch. vhost_set_backend_type() gets called only in vhost.c, so we can move the function there and make it static. We can then extern the visibility of kernel_ops, to match the other VhostOps in vhost-backend.h. The VhostOps constants now make more sense in vhost.h Suggested-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Signed-off-by: Tiberiu Georgescu <tiberiu.georgescu@nutanix.com> Message-Id: <20210809134015.67941-1-tiberiu.georgescu@nutanix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04hw/acpi: define PIIX4 acpi pci hotplug property strings at a single placeAni Sinha1-0/+2
Now that we have "acpi-pci-hotplug-with-bridge-support" PIIX4 PM property being used for both q35 and i440fx machine types, it is better that we defined this property string at a single place within a header file like other PIIX4 properties. We can then use this single definition at all the places that needs it instead of duplicating the string everywhere. While at it, this change also adds a definition for "acpi-root-pci-hotplug" PIIX4 PM property and uses this definition at all places that were formally using the string value. Signed-off-by: Ani Sinha <ani@anisinha.ca> Message-Id: <20210816083214.105740-1-ani@anisinha.ca> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04vhost-vdpa: Do not send empty IOTLB update batchesEugenio Pérez1-0/+1
With the introduction of the batch hinting, meaningless batches can be created with no IOTLB updates if the memory region was skipped by vhost_vdpa_listener_skipped_section. This is the case of host notifiers memory regions, device un/realize, and others. This causes the vdpa device to receive dma mapping settings with no changes, a possibly expensive operation for nothing. To avoid that, VHOST_IOTLB_BATCH_BEGIN hint is delayed until we have a meaningful (not skipped section) mapping or unmapping operation, and VHOST_IOTLB_BATCH_END is not written unless at least one of _UPDATE / _INVALIDATE has been issued. v3: * Use a bool instead of a counter avoiding potential number wrapping * Fix bad check on _commit * Move VHOST_BACKEND_F_IOTLB_BATCH check to vhost_vdpa_iotlb_batch_begin_once v2 (from RFC): * Rename misleading name * Abstract start batching function for listener_add/del Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Message-Id: <20210812140933.226288-1-eperezma@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-03Merge remote-tracking branch 'remotes/stsquad/tags/pull-for-6.2-020921-1' ↵Peter Maydell1-0/+13
into staging Testing and plugin updates: - fix typo in execlog plugin - clean-up and document gitlab FOO_RUNNER_AVAILABLE vars - fix plugin build issue on OSX and modules - add multi-core support to cache modelling plugin - clean-ups for plugin arg=FOO handling # gpg: Signature made Thu 02 Sep 2021 11:33:02 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-for-6.2-020921-1: (22 commits) docs/devel: be consistent about example plugin names docs/deprecated: deprecate passing plugin args through `arg=` tests/plugins/syscalls: adhere to new arg-passing scheme tests/plugins/mem: introduce "track" arg and make args not positional tests/plugins/insn: made arg inline not positional and parse it as bool tests/plugins/bb: adapt to the new arg passing scheme docs/tcg-plugins: new passing parameters scheme for cache docs plugins/howvec: adapting to the new argument passing scheme plugins/hwprofile: adapt to the new plugin arguments scheme plugins/lockstep: make socket path not positional & parse bool arg plugins/hotblocks: Added correct boolean argument parsing plugins/hotpages: introduce sortby arg and parsed bool args correctly plugins/api: added a boolean parsing plugin api plugins: allow plugin arguments to be passed directly docs/devel/tcg-plugins: added cores arg to cache plugin plugins: sort exported symbol list plugins/cache: supported multicore cache modelling plugins: do not limit exported symbols if modules are active gitlab-ci: Fix ..._RUNNER_AVAILABLE variables and document them gitlab-ci: Remove superfluous "dnf install" statement ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-02Merge remote-tracking branch 'remotes/hreitz/tags/pull-block-2021-09-01' ↵Peter Maydell4-2/+8
into staging Block patches: - Make the backup-top filter driver available for user-created block nodes (i.e. via blockdev-add) - Allow running iotests with gdb or valgrind being attached to qemu instances - Fix the raw format driver's permissions: There is no metadata, so we only need WRITE or RESIZE when the parent needs it - Basic reopen implementation for win32 files (file-win32.c) so that qemu-img commit can work - uclibc/musl build fix for the FUSE export code - Some iotests delinting - block-hmp-cmds.c refactoring # gpg: Signature made Wed 01 Sep 2021 16:01:54 BST # gpg: using RSA key CB62D7A0EE3829E45F004D34A1FA40D098019CDF # gpg: issuer "hreitz@redhat.com" # gpg: Good signature from "Hanna Reitz <hreitz@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: CB62 D7A0 EE38 29E4 5F00 4D34 A1FA 40D0 9801 9CDF * remotes/hreitz/tags/pull-block-2021-09-01: (56 commits) block/file-win32: add reopen handlers block/export/fuse.c: fix fuse-lseek on uclibc or musl block/block-copy: block_copy_state_new(): drop extra arguments iotests/image-fleecing: add test-case for copy-before-write filter iotests/image-fleecing: prepare for adding new test-case iotests/image-fleecing: rename tgt_node iotests/image-fleecing: proper source device iotests.py: hmp_qemu_io: support qdev iotests: move 222 to tests/image-fleecing iotests/222: constantly use single quotes for strings iotests/222: fix pylint and mypy complains python:QEMUMachine: template typing for self returning methods python/qemu/machine: QEMUMachine: improve qmp() method python/qemu/machine.py: refactor _qemu_args() qapi: publish copy-before-write filter block/copy-before-write: make public block driver block/block-copy: make setting progress optional block/copy-before-write: initialize block-copy bitmap block/copy-before-write: cbw_init(): use options block/copy-before-write: bdrv_cbw_append(): drop unused compress arg ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-02plugins/api: added a boolean parsing plugin apiMahmoud Mandour1-0/+13
This call will help boolean argument parsing since arguments are now passed to plugins as a name and value. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210730135817.17816-3-ma.mandourr@gmail.com> [AJB: add to symbols] Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2021-09-01Merge remote-tracking branch ↵Peter Maydell13-31/+189
'remotes/pmaydell/tags/pull-target-arm-20210901' into staging * Refactor M-profile systick to use Clocks instead of system_clock_scale global * clock: Provide builtin multiplier/divider * Add A64FX processor model * Enable MVE emulation in Cortex-M55 * hw: Add compat machines for 6.2 * hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans * hw/arm/raspi: Remove deprecated raspi2/raspi3 aliases # gpg: Signature made Wed 01 Sep 2021 11:35:57 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210901: (51 commits) arm: Remove system_clock_scale global hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale hw/arm/stellaris: Split stellaris-gptm into its own file hw/arm/stellaris: Fix code style issues in GPTM code hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale hw/arm/msf2-soc: Wire up refclk hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property hw/arm/msf2_soc: Don't allocate separate MemoryRegions hw/arm/stellaris: Wire sysclk up to armv7m hw/arm/stellaris: split stellaris_sys_init() hw/arm/nrf51: Wire up sysclk hw/arm/stm32vldiscovery: Delete trailing blank line hw/arm/stm32f405: Wire up sysclk and refclk hw/arm/stm32f205: Wire up sysclk and refclk hw/arm/stm32f100: Wire up sysclk and refclk hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize clock: Provide builtin multiplier/divider hw/arm/mps2.c: Connect up armv7m clocks armsse: Wire up systick cpuclk clock hw/arm/armv7m: Create input clocks ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01block/block-copy: block_copy_state_new(): drop extra argumentsVladimir Sementsov-Ogievskiy1-1/+0
The only caller pass copy_range and compress both false. Let's just drop these arguments. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20210824083856.17408-35-vsementsov@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01block/backup: move cluster size calculation to block-copyVladimir Sementsov-Ogievskiy1-2/+3
The main consumer of cluster-size is block-copy. Let's calculate it here instead of passing through backup-top. We are going to publish copy-before-write filter soon, so it will be created through options. But we don't want for now to make explicit option for cluster-size, let's continue to calculate it automatically. So, now is the time to get rid of cluster_size argument for bdrv_cbw_append(). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20210824083856.17408-10-vsementsov@virtuozzo.com> [hreitz: Add qemu/error-report.h include to block/block-copy.c] Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01block/block-copy: introduce block_copy_set_copy_opts()Vladimir Sementsov-Ogievskiy1-0/+3
We'll need a possibility to set compress and use_copy_range options after initialization of the state. So make corresponding part of block_copy_state_new() separate and public. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20210824083856.17408-8-vsementsov@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01block-copy: move detecting fleecing scheme to block-copyVladimir Sementsov-Ogievskiy1-2/+1
We want to simplify initialization interface of copy-before-write filter as we are going to make it public. So, let's detect fleecing scheme exactly in block-copy code, to not pass this information through extra levels. Why not just set BDRV_REQ_SERIALISING unconditionally: because we are going to implement new more efficient fleecing scheme which will not rely on backing feature. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20210824083856.17408-7-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01qdev-properties: PropertyInfo: add realized_set_allowed fieldVladimir Sementsov-Ogievskiy1-0/+1
Add field, so property can declare support for setting the property when device is realized. To be used in the following commit. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20210824083856.17408-4-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01block: introduce blk_replace_bsVladimir Sementsov-Ogievskiy1-0/+1
Add function to change bs inside blk. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20210824083856.17408-3-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01block: introduce bdrv_replace_child_bs()Vladimir Sementsov-Ogievskiy1-0/+2
Add function to transactionally replace bs inside BdrvChild. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20210824083856.17408-2-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01arm: Remove system_clock_scale globalPeter Maydell1-22/+0
All the devices that used to use system_clock_scale have now been converted to use Clock inputs instead, so the global is no longer needed; remove it and all the code that sets it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210812093356.1946-26-peter.maydell@linaro.org
2021-09-01hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scalePeter Maydell1-0/+3
The stellaris-gptm timer currently uses system_clock_scale for one of its timer modes where the timer runs at the CPU clock rate. Make it use a Clock input instead. We don't try to make the timer handle changes in the clock frequency while the downcounter is running. This is not a change in behaviour from the previous system_clock_scale implementation -- we will pick up the new frequency only when the downcounter hits zero. Handling dynamic clock changes when the counter is running would require state that the current gptm implementation doesn't have. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-25-peter.maydell@linaro.org
2021-09-01hw/arm/stellaris: Split stellaris-gptm into its own filePeter Maydell1-0/+48
The implementation of the Stellaris general purpose timer module device stellaris-gptm is currently in the same source file as the board model. Split it out into its own source file in hw/timer. Apart from the new file comment headers and the Kconfig and meson.build changes, this is just code movement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-24-peter.maydell@linaro.org
2021-09-01hw/arm/msf2-soc: Wire up refclkPeter Maydell1-0/+1
Wire up the refclk for the msf2 SoC. This SoC runs the refclk at a frequency which is programmably either /4, /8, /16 or /32 of the main CPU clock. We don't currently model the register which allows the guest to set the divisor, so implement the refclk as a fixed /32 of the CPU clock (which is the value of the divisor at reset). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-21-peter.maydell@linaro.org
2021-09-01hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk propertyPeter Maydell1-1/+2
Instead of passing the MSF2 SoC an integer property specifying the CPU clock rate, pass it a Clock instead. This lets us wire that clock up to the armv7m object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-20-peter.maydell@linaro.org
2021-09-01hw/arm/msf2_soc: Don't allocate separate MemoryRegionsPeter Maydell1-0/+4
In the realize method of the msf2-soc SoC object, we call g_new() to create new MemoryRegion objects for the nvm, nvm_alias, and sram. This is unnecessary; make these MemoryRegions member fields of the device state struct instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-19-peter.maydell@linaro.org
2021-09-01hw/arm/nrf51: Wire up sysclkPeter Maydell1-0/+2
Wire up the sysclk input to the armv7m object. Strictly this SoC should not have a systick device at all, but our armv7m container object doesn't currently support disabling the systick device. For the moment, add a TODO comment, but note that this is why we aren't wiring up a refclk (no need for one). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-16-peter.maydell@linaro.org
2021-09-01hw/arm/stm32f405: Wire up sysclk and refclkPeter Maydell1-0/+3
Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the netduinoplus2 board where the systick reference clock was running at 1MHz rather than 21MHz. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-14-peter.maydell@linaro.org
2021-09-01hw/arm/stm32f205: Wire up sysclk and refclkPeter Maydell1-0/+4
Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the netduino2 board where the systick reference clock was running at 1MHz rather than 15MHz. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-13-peter.maydell@linaro.org
2021-09-01hw/arm/stm32f100: Wire up sysclk and refclkPeter Maydell1-0/+4
Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the stm32vldiscovery board where the systick reference clock was running at 1MHz rather than 3MHz. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-12-peter.maydell@linaro.org
2021-09-01hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realizePeter Maydell2-0/+8
In the realize methods of the stm32f100 and stm32f205 SoC objects, we call g_new() to create new MemoryRegion objects for the sram, flash, and flash_alias. This is unnecessary (and leaves open the possibility of leaking the allocations if we exit from realize with an error). Make these MemoryRegions member fields of the device state struct instead, as stm32f405 already does. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-11-peter.maydell@linaro.org
2021-09-01clock: Provide builtin multiplier/dividerPeter Maydell1-0/+29
It is quite common for a clock tree to involve possibly programmable clock multipliers or dividers, where the frequency of a clock is for instance divided by 8 to produce a slower clock to feed to a particular device. Currently we provide no convenient mechanism for modelling this. You can implement it by having an input Clock and an output Clock, and manually setting the period of the output clock in the period-changed callback of the input clock, but that's quite clunky. This patch adds support in the Clock objects themselves for setting a multiplier or divider. The effect of setting this on a clock is that when the clock's period is changed, all the children of the clock are set to period * multiplier / divider, rather than being set to the same period as the parent clock. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-10-peter.maydell@linaro.org
2021-09-01hw/arm/armv7m: Create input clocksPeter Maydell1-0/+6
Create input clocks on the armv7m container object which pass through to the systick timers, so that users of the armv7m object can specify the clocks being used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-7-peter.maydell@linaro.org
2021-09-01hw/timer/armv7m_systick: Add input clocksPeter Maydell1-0/+7
The v7M systick timer can be programmed to run from either of two clocks: * an "external reference clock" (when SYST_CSR.CLKSOURCE == 0) * the main CPU clock (when SYST_CSR.CLKSOURCE == 1) Our implementation currently hardwires the external reference clock to be 1MHz, and allows boards to set the main CPU clock frequency via the global 'system_clock_scale'. (Most boards set that to a constant value; the Stellaris boards allow the guest to reprogram it via the board-specific RCC registers). As the first step in converting this to use the Clock infrastructure, add input clocks to the systick device for the reference clock and the CPU clock. The device implementation ignores them; once we have made all the users of the device correctly wire up the new Clocks we will switch the implementation to use them and ignore the old system_clock_scale. This is a migration compat break for all M-profile boards, because of the addition of the new clock objects to the vmstate struct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-6-peter.maydell@linaro.org
2021-09-01hw/timer/armv7m_systick: Add usual QEMU interface commentPeter Maydell1-0/+7
Add the usual-style QEMU interface comment documenting what properties, etc, this device exposes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-5-peter.maydell@linaro.org
2021-09-01arm: Move system PPB container handling to armv7mPeter Maydell2-3/+4
Instead of having the NVIC device provide a single sysbus memory region covering the whole of the "System PPB" space, which implements the default behaviour for unimplemented ranges and provides the NS alias window to the sysregs as well as the main sysreg MR, move this handling to the container armv7m device. The NVIC now provides a single memory region which just implements the system registers. This consolidates all the handling of "map various devices in the PPB" into the armv7m container where it belongs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-4-peter.maydell@linaro.org
2021-09-01arm: Move systick device creation from NVIC to ARMv7M objectPeter Maydell2-4/+12
There's no particular reason why the NVIC should be owning the SysTick device objects; move them into the ARMv7M container object instead, as part of consolidating the "create the devices which are built into an M-profile CPU and map them into their architected locations in the address space" work into one place. This involves temporarily creating a duplicate copy of the nvic_sysreg_ns_ops struct and its read/write functions (renamed as v7m_sysreg_ns_*), but we will delete the NVIC's copy of this code in a subsequent patch. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-3-peter.maydell@linaro.org
2021-09-01arm: Move M-profile RAS register block into its own devicePeter Maydell3-1/+39
Currently we implement the RAS register block within the NVIC device. It isn't really very tightly coupled with the NVIC proper, so instead move it out into a sysbus device of its own and have the top level ARMv7M container create it and map it into memory at the right address. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-2-peter.maydell@linaro.org
2021-09-01hw: Add compat machines for 6.2Yanan Wang2-0/+6
Add 6.2 machine types for arm/i440fx/q35/s390x/spapr. Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01Merge remote-tracking branch 'remotes/kraxel/tags/vga-20210901-pull-request' ↵Peter Maydell1-0/+2
into staging vga: misc fixes and cleanups. # gpg: Signature made Wed 01 Sep 2021 05:18:46 BST # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20210901-pull-request: hw/display/artist: Fix bug in coordinate extraction in artist_vram_read() and artist_vram_write() hw/display/xlnx_dp: fix an out-of-bounds read in xlnx_dp_read vga: don't abort when adding a duplicate isa-vga device ui/console: Restrict udmabuf_fd() to Linux hw/display: Restrict virtio-gpu-udmabuf stubs to !Linux virtio-gpu: no point of checking res->iov Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01hw/registerfields: Use 64-bit bitfield for FIELD_DP64Joe Komlodi1-1/+1
If we have a field that's wider than 32-bits, we need a data type wide enough to be able to create the bitfield used to deposit the value. Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1626805903-162860-3-git-send-email-joe.komlodi@xilinx.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01hw/core/register: Add more 64-bit utilitiesJoe Komlodi2-0/+16
We already have some utilities to handle 64-bit wide registers, so this just adds some more for: - Initializing 64-bit registers - Extracting and depositing to an array of 64-bit registers Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1626805903-162860-2-git-send-email-joe.komlodi@xilinx.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-08-31ui/gtk-clipboard: use qemu_clipboard_info helperMarc-André Lureau1-1/+0
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210805135715.857938-16-marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-08-31ui/clipboard: add qemu_clipboard_peer_release() helperMarc-André Lureau1-0/+11
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210805135715.857938-8-marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-08-31ui/clipboard: add qemu_clipboard_peer_owns() helperMarc-André Lureau1-0/+11
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210805135715.857938-7-marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-08-31ui/clipboard: add helper to retrieve current clipboardMarc-André Lureau1-0/+9
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210805135715.857938-6-marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-08-31ui/vdagent: fix leak on error pathMarc-André Lureau1-0/+2
"info" was leaked when more than 10 entries. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210805135715.857938-2-marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-08-31ui/console: Restrict udmabuf_fd() to LinuxPhilippe Mathieu-Daudé1-0/+2
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210823100454.615816-3-philmd@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-08-27include/qemu/int128.h: introduce bswap128sMatheus Ferst1-1/+16
Changes the current bswap128 implementation to use __builtin_bswap128 when available, adds a bswap128 implementation for !CONFIG_INT128 builds, and introduces bswap128s based on bswap128. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210826145656.2507213-2-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
generated by cgit v1.1 at 2025-01-17 06:21:50 +0000