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2021-09-13hw/intc: GICv3 redistributor ITS processingShashi Mallela1-0/+7
Implemented lpi processing at redistributor to get lpi config info from lpi configuration table,determine priority,set pending state in lpi pending table and forward the lpi to cpuif.Added logic to invoke redistributor lpi processing with translated LPI which set/clear LPI from ITS device as part of ITS INT,CLEAR,DISCARD command and GITS_TRANSLATER processing. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210910143951.92242-7-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-13hw/intc: GICv3 ITS Feature enablementShashi Mallela1-0/+1
Added properties to enable ITS feature and define qemu system address space memory in gicv3 common,setup distributor and redistributor registers to indicate LPI support. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-6-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-13hw/intc: GICv3 ITS Command processingShashi Mallela1-0/+2
Added ITS command queue handling for MAPTI,MAPI commands,handled ITS translation which triggers an LPI via INT command as well as write to GITS_TRANSLATER register,defined enum to differentiate between ITS command interrupt trigger and GITS_TRANSLATER based interrupt trigger. Each of these commands make use of other functionalities implemented to get device table entry,collection table entry or interrupt translation table entry required for their processing. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210910143951.92242-5-shashi.mallela@linaro.org [PMM: use INTERRUPT for ItsCmdType enum name to avoid conflict with INT type defined by Windows headers] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-13hw/intc: GICv3 ITS register definitions addedShashi Mallela2-0/+26
Defined descriptors for ITS device table,collection table and ITS command queue entities.Implemented register read/write functions, extract ITS table parameters and command queue parameters,extended gicv3 common to capture qemu address space(which host the ITS table platform memories required for subsequent ITS processing) and initialize the same in ITS device. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-3-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-13hw/intc: GICv3 ITS initial frameworkShashi Mallela1-1/+8
Added register definitions relevant to ITS,implemented overall ITS device framework with stubs for ITS control and translater regions read/write,extended ITS common to handle mmio init between existing kvm device and newer qemu device. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-2-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-10Merge remote-tracking branch 'remotes/vivier/tags/q800-pull-request' into ↵Peter Maydell1-51/+50
staging q800 pull request 20210908 mac_via: remove MAC_VIA device and prepare for Nubus IRQs # gpg: Signature made Wed 08 Sep 2021 16:35:03 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/q800-pull-request: mac_via: add qdev gpios for nubus slot interrupts to VIA2 mac_via: rename VIA2_IRQ_SLOT_BIT to VIA2_IRQ_NUBUS_BIT mac_via: remove explicit viaN prefix from VIA IRQ gpios mac_via: remove mac_via device mac_via: move VIA1 realize logic from mac_via_realize() to mos6522_q800_via1_realize() mac_via: move VIA1 reset logic from mac_via_reset() to mos6522_q800_via1_reset() mac_via: move q800 VIA1 timer variables to q800 VIA1 VMStateDescription mac_via: move ADB variables to MOS6522Q800VIA1State mac_via: move PRAM/RTC variables to MOS6522Q800VIA1State mac_via: move PRAM contents and block backend to MOS6522Q800VIA1State mac_via: move last_b variable into q800 VIA1 VMStateDescription mac_via: introduce new VMStateDescription for q800 VIA1 and VIA2 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-08mac_via: add qdev gpios for nubus slot interrupts to VIA2Mark Cave-Ayland1-0/+10
These will soon be required to enable nubus devices to support interrupts. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210830102447.10806-13-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08mac_via: rename VIA2_IRQ_SLOT_BIT to VIA2_IRQ_NUBUS_BITMark Cave-Ayland1-11/+11
Also improve the alignment of the shifted constants. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210830102447.10806-12-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08mac_via: remove mac_via deviceMark Cave-Ayland1-16/+5
Remove the mac_via device and wire up both q800 VIA1 and VIA2 directly for the m68k q800 machine. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210830102447.10806-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08mac_via: move ADB variables to MOS6522Q800VIA1StateMark Cave-Ayland1-10/+10
The ADB is accessed using clock and data pins on q800 VIA1 port B and so can be moved to MOS6522Q800VIA1State. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210830102447.10806-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08mac_via: move PRAM/RTC variables to MOS6522Q800VIA1StateMark Cave-Ayland1-11/+10
The PRAM/RTC is accessed using clock and data pins on q800 VIA1 port B and so can be moved to MOS6522Q800VIA1State. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210830102447.10806-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08mac_via: move PRAM contents and block backend to MOS6522Q800VIA1StateMark Cave-Ayland1-3/+4
The PRAM contents are accessed using clock and data pins on q800 VIA1 port B and so can be moved to MOS6522Q800VIA1State. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210830102447.10806-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08tcg: Drop gen_io_end()Peter Maydell1-17/+10
Now we have removed all the uses of gen_io_end() from target frontends, the only callsite is inside gen_tb_start(). Inline the code there, and remove the reference to it from the documentation. While we are inlining the code, switch it to use tcg_constant_i32() so we don't have to manually create and destroy a TCG temporary. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210724134902.7785-3-peter.maydell@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-09-07Merge remote-tracking branch ↵Peter Maydell3-6/+67
'remotes/thuth-gitlab/tags/s390x-pull-request-2021-09-07' into staging * Some CSS related fixes * Storage key related fixes * Test SIGILL and SIGSEGV handling in usermode emulation * Fix SETPREFIX instruction * Replace PAGE_SIZE, PAGE_SHIFT and PAGE_MASK to fix Alpine compilation * Add more feature to gen16 default model # gpg: Signature made Tue 07 Sep 2021 14:07:38 BST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/thuth-gitlab/tags/s390x-pull-request-2021-09-07: s390x/cpumodel: Add more feature to gen16 default model s390x: Replace PAGE_SIZE, PAGE_SHIFT and PAGE_MASK hw/s390x/s390-skeys: lazy storage key enablement under TCG hw/s390x/s390-skeys: rename skeys_enabled to skeys_are_enabled hw/s390x/s390-skeys: check if an address is valid before dumping the key hw/s390x/s390-skeys: use memory mapping to detect which storage keys to dump hw/s390x/s390-skeys: use memory mapping to detect which storage keys to migrate s390x/mmu_helper: avoid setting the storage key if nothing changed s390x/mmu_helper: move address validation into mmu_translate*() s390x/mmu_helper: fixup mmu_translate() documentation s390x/mmu_helper: no need to pass access type to mmu_translate_asce() s390x/tcg: check for addressing exceptions for RRBE, SSKE and ISKE s390x/tcg: convert real to absolute address for RRBE, SSKE and ISKE s390x/tcg: fix ignoring bit 63 when setting the storage key in SSKE s390x/tcg: wrap address for RRBE s390x/ioinst: Fix wrong MSCH alignment check on little endian s390x/tcg: fix and optimize SPX (SET PREFIX) tests/tcg/s390x: Test SIGILL and SIGSEGV handling css: fix actl handling for unit exceptions vfio-ccw: forward halt/clear errors Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-07util/vfio-helpers: Pass Error handle to qemu_vfio_dma_map()Philippe Mathieu-Daudé1-1/+1
Currently qemu_vfio_dma_map() displays errors on stderr. When using management interface, this information is simply lost. Pass qemu_vfio_dma_map() an Error** handle so it can propagate the error to callers. Reviewed-by: Fam Zheng <fam@euphon.net> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20210902070025.197072-7-philmd@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-09-06s390x: Replace PAGE_SIZE, PAGE_SHIFT and PAGE_MASKThomas Huth1-4/+1
The PAGE_SIZE macro is causing trouble on Alpine Linux since it clashes with a macro from a system header there. We already have the TARGET_PAGE_SIZE, TARGET_PAGE_MASK and TARGET_PAGE_BITS macros in QEMU anyway, so let's simply replace the PAGE_SIZE, PAGE_MASK and PAGE_SHIFT macro with their TARGET_* counterparts. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/572 Message-Id: <20210901125800.611183-1-thuth@redhat.com> Reviewed-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-09-06hw/s390x/s390-skeys: lazy storage key enablement under TCGDavid Hildenbrand1-0/+63
Let's enable storage keys lazily under TCG, just as we do under KVM. Only fairly old Linux versions actually make use of storage keys, so it can be kind of wasteful to allocate quite some memory and track changes and references if nobody cares. We have to make sure to flush the TLB when enabling storage keys after the VM was already running: otherwise it might happen that we don't catch references or modifications afterwards. Add proper documentation to all callbacks. The kvm-unit-tests skey tests keeps on working with this change. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210903155514.44772-14-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-09-06hw/s390x/s390-skeys: rename skeys_enabled to skeys_are_enabledDavid Hildenbrand1-1/+1
... and make it return a bool instead. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210903155514.44772-13-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-09-06css: fix actl handling for unit exceptionsCornelia Huck1-1/+2
When a subchannel becomes pending with unit exception, start pending (and for that matter, halt or clear pending) are not removed in the actl. Device active and subchannel active, however, are (due to the subchannel becoming status pending with primary respectively secondary status). The other conditions in the actl are only cleared when the guest executes tsch on the subchannel. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com> Tested-by: Jared Rossi <jrossi@linux.ibm.com> Message-Id: <20210705163952.736020-3-cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-09-05Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell9-15/+12
pc,pci,virtio: fixes, cleanups Fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sat 04 Sep 2021 22:34:10 BST # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (35 commits) vhost-vdpa: remove the unncessary queue_index assignment vhost-vdpa: fix the wrong assertion in vhost_vdpa_init() vhost-vdpa: tweak the error label in vhost_vdpa_add() vhost-vdpa: fix leaking of vhost_net in vhost_vdpa_add() vhost-vdpa: don't cleanup twice in vhost_vdpa_add() vhost-vdpa: remove the unnecessary check in vhost_vdpa_add() vhost_net: do not assume nvqs is always 2 vhost: use unsigned int for nvqs vhost_net: remove the meaningless assignment in vhost_net_start_one() vhost-vdpa: correctly return err in vhost_vdpa_set_backend_cap() vhost-vdpa: remove unused variable "acked_features" tests/vhost-user-bridge.c: Fix typo in help message tests/vhost-user-bridge.c: Sanity check socket path length hw/virtio: Add flatview update in vhost_user_cleanup() hw/virtio: Remove NULL check in virtio_free_region_cache() hw/virtio: Document virtio_queue_packed_empty_rcu is called within RCU MAINTAINERS: Added myself as a reviewer for acpi/smbios subsystem hw/acpi: use existing references to pci device struct within functions hw/pci: remove all references to find_i440fx function hw/i386/acpi-build: Get NUMA information from struct NumaState ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-04vhost_net: do not assume nvqs is always 2Jason Wang1-0/+1
This patch switches to initialize dev.nvqs from the VhostNetOptions instead of assuming it was 2. This is useful for implementing control virtqueue support which will be a single vhost_net structure with a single cvq. Note that nvqs is still set to 2 for all users and this patch does not change functionality. Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Eli Cohen <elic@nvidia.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20210903091031.47303-6-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04vhost: use unsigned int for nvqsJason Wang1-1/+1
Switch to use unsigned int for nvqs since it's not expected to be negative. Reviewed-by: Eli Cohen <elic@nvidia.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20210903091031.47303-5-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04hw/pci: remove all references to find_i440fx functionAni Sinha1-1/+0
commit c0e427d6eb5fefc538 ("hw/acpi/ich9: Enable ACPI PCI hot-plug") removed all uses of find_i440fx() function. This has been replaced by the more generic call acpi_get_i386_pci_host() which maybe able to find the root bus both for i440fx machine type as well as for the q35 machine type. There seems to be no more any need to maintain a i440fx specific version of the api call. Remove it. Tested by building from a clean tree successfully. Signed-off-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210825031949.919376-2-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04hw/i386/acpi-build: Get NUMA information from struct NumaStateJingqi Liu1-4/+0
Since commits aa57020774b ("numa: move numa global variable nb_numa_nodes into MachineState") and 7e721e7b10e ("numa: move numa global variable numa_info into MachineState"), we can get NUMA information completely from MachineState::numa_state. Remove PCMachineState::numa_nodes and PCMachineState::node_mem, since they are just copied from MachineState::numa_state. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Jingqi Liu <jingqi.liu@intel.com> Message-Id: <20210823011254.28506-1-jingqi.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04virtio-bus: introduce iommu_enabled()Jason Wang1-1/+3
This patch introduce a new method for the virtio-bus for the transport to report whether or not the IOMMU is enabled for the device. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20210804034803.1644-2-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04acpi: Delete broken ACPI_GED_X86 macroEduardo Habkost1-2/+0
The macro never worked and never will, because the AcpiGedX86State type never existed. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20210805193431.307761-2-ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04hw/virtio: move vhost_set_backend_type() to vhost.cTiberiu Georgescu2-6/+4
Just a small refactor patch. vhost_set_backend_type() gets called only in vhost.c, so we can move the function there and make it static. We can then extern the visibility of kernel_ops, to match the other VhostOps in vhost-backend.h. The VhostOps constants now make more sense in vhost.h Suggested-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Signed-off-by: Tiberiu Georgescu <tiberiu.georgescu@nutanix.com> Message-Id: <20210809134015.67941-1-tiberiu.georgescu@nutanix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04hw/acpi: define PIIX4 acpi pci hotplug property strings at a single placeAni Sinha1-0/+2
Now that we have "acpi-pci-hotplug-with-bridge-support" PIIX4 PM property being used for both q35 and i440fx machine types, it is better that we defined this property string at a single place within a header file like other PIIX4 properties. We can then use this single definition at all the places that needs it instead of duplicating the string everywhere. While at it, this change also adds a definition for "acpi-root-pci-hotplug" PIIX4 PM property and uses this definition at all places that were formally using the string value. Signed-off-by: Ani Sinha <ani@anisinha.ca> Message-Id: <20210816083214.105740-1-ani@anisinha.ca> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04vhost-vdpa: Do not send empty IOTLB update batchesEugenio Pérez1-0/+1
With the introduction of the batch hinting, meaningless batches can be created with no IOTLB updates if the memory region was skipped by vhost_vdpa_listener_skipped_section. This is the case of host notifiers memory regions, device un/realize, and others. This causes the vdpa device to receive dma mapping settings with no changes, a possibly expensive operation for nothing. To avoid that, VHOST_IOTLB_BATCH_BEGIN hint is delayed until we have a meaningful (not skipped section) mapping or unmapping operation, and VHOST_IOTLB_BATCH_END is not written unless at least one of _UPDATE / _INVALIDATE has been issued. v3: * Use a bool instead of a counter avoiding potential number wrapping * Fix bad check on _commit * Move VHOST_BACKEND_F_IOTLB_BATCH check to vhost_vdpa_iotlb_batch_begin_once v2 (from RFC): * Rename misleading name * Abstract start batching function for listener_add/del Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Message-Id: <20210812140933.226288-1-eperezma@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-03Merge remote-tracking branch 'remotes/stsquad/tags/pull-for-6.2-020921-1' ↵Peter Maydell1-0/+13
into staging Testing and plugin updates: - fix typo in execlog plugin - clean-up and document gitlab FOO_RUNNER_AVAILABLE vars - fix plugin build issue on OSX and modules - add multi-core support to cache modelling plugin - clean-ups for plugin arg=FOO handling # gpg: Signature made Thu 02 Sep 2021 11:33:02 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-for-6.2-020921-1: (22 commits) docs/devel: be consistent about example plugin names docs/deprecated: deprecate passing plugin args through `arg=` tests/plugins/syscalls: adhere to new arg-passing scheme tests/plugins/mem: introduce "track" arg and make args not positional tests/plugins/insn: made arg inline not positional and parse it as bool tests/plugins/bb: adapt to the new arg passing scheme docs/tcg-plugins: new passing parameters scheme for cache docs plugins/howvec: adapting to the new argument passing scheme plugins/hwprofile: adapt to the new plugin arguments scheme plugins/lockstep: make socket path not positional & parse bool arg plugins/hotblocks: Added correct boolean argument parsing plugins/hotpages: introduce sortby arg and parsed bool args correctly plugins/api: added a boolean parsing plugin api plugins: allow plugin arguments to be passed directly docs/devel/tcg-plugins: added cores arg to cache plugin plugins: sort exported symbol list plugins/cache: supported multicore cache modelling plugins: do not limit exported symbols if modules are active gitlab-ci: Fix ..._RUNNER_AVAILABLE variables and document them gitlab-ci: Remove superfluous "dnf install" statement ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-02Merge remote-tracking branch 'remotes/hreitz/tags/pull-block-2021-09-01' ↵Peter Maydell4-2/+8
into staging Block patches: - Make the backup-top filter driver available for user-created block nodes (i.e. via blockdev-add) - Allow running iotests with gdb or valgrind being attached to qemu instances - Fix the raw format driver's permissions: There is no metadata, so we only need WRITE or RESIZE when the parent needs it - Basic reopen implementation for win32 files (file-win32.c) so that qemu-img commit can work - uclibc/musl build fix for the FUSE export code - Some iotests delinting - block-hmp-cmds.c refactoring # gpg: Signature made Wed 01 Sep 2021 16:01:54 BST # gpg: using RSA key CB62D7A0EE3829E45F004D34A1FA40D098019CDF # gpg: issuer "hreitz@redhat.com" # gpg: Good signature from "Hanna Reitz <hreitz@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: CB62 D7A0 EE38 29E4 5F00 4D34 A1FA 40D0 9801 9CDF * remotes/hreitz/tags/pull-block-2021-09-01: (56 commits) block/file-win32: add reopen handlers block/export/fuse.c: fix fuse-lseek on uclibc or musl block/block-copy: block_copy_state_new(): drop extra arguments iotests/image-fleecing: add test-case for copy-before-write filter iotests/image-fleecing: prepare for adding new test-case iotests/image-fleecing: rename tgt_node iotests/image-fleecing: proper source device iotests.py: hmp_qemu_io: support qdev iotests: move 222 to tests/image-fleecing iotests/222: constantly use single quotes for strings iotests/222: fix pylint and mypy complains python:QEMUMachine: template typing for self returning methods python/qemu/machine: QEMUMachine: improve qmp() method python/qemu/machine.py: refactor _qemu_args() qapi: publish copy-before-write filter block/copy-before-write: make public block driver block/block-copy: make setting progress optional block/copy-before-write: initialize block-copy bitmap block/copy-before-write: cbw_init(): use options block/copy-before-write: bdrv_cbw_append(): drop unused compress arg ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-02plugins/api: added a boolean parsing plugin apiMahmoud Mandour1-0/+13
This call will help boolean argument parsing since arguments are now passed to plugins as a name and value. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210730135817.17816-3-ma.mandourr@gmail.com> [AJB: add to symbols] Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2021-09-01Merge remote-tracking branch ↵Peter Maydell13-31/+189
'remotes/pmaydell/tags/pull-target-arm-20210901' into staging * Refactor M-profile systick to use Clocks instead of system_clock_scale global * clock: Provide builtin multiplier/divider * Add A64FX processor model * Enable MVE emulation in Cortex-M55 * hw: Add compat machines for 6.2 * hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans * hw/arm/raspi: Remove deprecated raspi2/raspi3 aliases # gpg: Signature made Wed 01 Sep 2021 11:35:57 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210901: (51 commits) arm: Remove system_clock_scale global hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale hw/arm/stellaris: Split stellaris-gptm into its own file hw/arm/stellaris: Fix code style issues in GPTM code hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale hw/arm/msf2-soc: Wire up refclk hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property hw/arm/msf2_soc: Don't allocate separate MemoryRegions hw/arm/stellaris: Wire sysclk up to armv7m hw/arm/stellaris: split stellaris_sys_init() hw/arm/nrf51: Wire up sysclk hw/arm/stm32vldiscovery: Delete trailing blank line hw/arm/stm32f405: Wire up sysclk and refclk hw/arm/stm32f205: Wire up sysclk and refclk hw/arm/stm32f100: Wire up sysclk and refclk hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize clock: Provide builtin multiplier/divider hw/arm/mps2.c: Connect up armv7m clocks armsse: Wire up systick cpuclk clock hw/arm/armv7m: Create input clocks ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01block/block-copy: block_copy_state_new(): drop extra argumentsVladimir Sementsov-Ogievskiy1-1/+0
The only caller pass copy_range and compress both false. Let's just drop these arguments. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20210824083856.17408-35-vsementsov@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01block/backup: move cluster size calculation to block-copyVladimir Sementsov-Ogievskiy1-2/+3
The main consumer of cluster-size is block-copy. Let's calculate it here instead of passing through backup-top. We are going to publish copy-before-write filter soon, so it will be created through options. But we don't want for now to make explicit option for cluster-size, let's continue to calculate it automatically. So, now is the time to get rid of cluster_size argument for bdrv_cbw_append(). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20210824083856.17408-10-vsementsov@virtuozzo.com> [hreitz: Add qemu/error-report.h include to block/block-copy.c] Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01block/block-copy: introduce block_copy_set_copy_opts()Vladimir Sementsov-Ogievskiy1-0/+3
We'll need a possibility to set compress and use_copy_range options after initialization of the state. So make corresponding part of block_copy_state_new() separate and public. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20210824083856.17408-8-vsementsov@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01block-copy: move detecting fleecing scheme to block-copyVladimir Sementsov-Ogievskiy1-2/+1
We want to simplify initialization interface of copy-before-write filter as we are going to make it public. So, let's detect fleecing scheme exactly in block-copy code, to not pass this information through extra levels. Why not just set BDRV_REQ_SERIALISING unconditionally: because we are going to implement new more efficient fleecing scheme which will not rely on backing feature. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20210824083856.17408-7-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01qdev-properties: PropertyInfo: add realized_set_allowed fieldVladimir Sementsov-Ogievskiy1-0/+1
Add field, so property can declare support for setting the property when device is realized. To be used in the following commit. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20210824083856.17408-4-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01block: introduce blk_replace_bsVladimir Sementsov-Ogievskiy1-0/+1
Add function to change bs inside blk. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20210824083856.17408-3-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01block: introduce bdrv_replace_child_bs()Vladimir Sementsov-Ogievskiy1-0/+2
Add function to transactionally replace bs inside BdrvChild. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20210824083856.17408-2-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01arm: Remove system_clock_scale globalPeter Maydell1-22/+0
All the devices that used to use system_clock_scale have now been converted to use Clock inputs instead, so the global is no longer needed; remove it and all the code that sets it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210812093356.1946-26-peter.maydell@linaro.org
2021-09-01hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scalePeter Maydell1-0/+3
The stellaris-gptm timer currently uses system_clock_scale for one of its timer modes where the timer runs at the CPU clock rate. Make it use a Clock input instead. We don't try to make the timer handle changes in the clock frequency while the downcounter is running. This is not a change in behaviour from the previous system_clock_scale implementation -- we will pick up the new frequency only when the downcounter hits zero. Handling dynamic clock changes when the counter is running would require state that the current gptm implementation doesn't have. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-25-peter.maydell@linaro.org
2021-09-01hw/arm/stellaris: Split stellaris-gptm into its own filePeter Maydell1-0/+48
The implementation of the Stellaris general purpose timer module device stellaris-gptm is currently in the same source file as the board model. Split it out into its own source file in hw/timer. Apart from the new file comment headers and the Kconfig and meson.build changes, this is just code movement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-24-peter.maydell@linaro.org
2021-09-01hw/arm/msf2-soc: Wire up refclkPeter Maydell1-0/+1
Wire up the refclk for the msf2 SoC. This SoC runs the refclk at a frequency which is programmably either /4, /8, /16 or /32 of the main CPU clock. We don't currently model the register which allows the guest to set the divisor, so implement the refclk as a fixed /32 of the CPU clock (which is the value of the divisor at reset). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-21-peter.maydell@linaro.org
2021-09-01hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk propertyPeter Maydell1-1/+2
Instead of passing the MSF2 SoC an integer property specifying the CPU clock rate, pass it a Clock instead. This lets us wire that clock up to the armv7m object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-20-peter.maydell@linaro.org
2021-09-01hw/arm/msf2_soc: Don't allocate separate MemoryRegionsPeter Maydell1-0/+4
In the realize method of the msf2-soc SoC object, we call g_new() to create new MemoryRegion objects for the nvm, nvm_alias, and sram. This is unnecessary; make these MemoryRegions member fields of the device state struct instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-19-peter.maydell@linaro.org
2021-09-01hw/arm/nrf51: Wire up sysclkPeter Maydell1-0/+2
Wire up the sysclk input to the armv7m object. Strictly this SoC should not have a systick device at all, but our armv7m container object doesn't currently support disabling the systick device. For the moment, add a TODO comment, but note that this is why we aren't wiring up a refclk (no need for one). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-16-peter.maydell@linaro.org
2021-09-01hw/arm/stm32f405: Wire up sysclk and refclkPeter Maydell1-0/+3
Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the netduinoplus2 board where the systick reference clock was running at 1MHz rather than 21MHz. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-14-peter.maydell@linaro.org
2021-09-01hw/arm/stm32f205: Wire up sysclk and refclkPeter Maydell1-0/+4
Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the netduino2 board where the systick reference clock was running at 1MHz rather than 15MHz. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-13-peter.maydell@linaro.org
2021-09-01hw/arm/stm32f100: Wire up sysclk and refclkPeter Maydell1-0/+4
Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the stm32vldiscovery board where the systick reference clock was running at 1MHz rather than 3MHz. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-12-peter.maydell@linaro.org
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