Age | Commit message (Expand) | Author | Files | Lines |
2020-09-17 | microvm: make virtio irq base runtime configurable | Gerd Hoffmann | 1 | -1/+1 |
2020-09-17 | acpi: move acpi_dsdt_add_power_button() to ged | Gerd Hoffmann | 1 | -0/+1 |
2020-09-17 | acpi: ged: add x86 device variant. | Gerd Hoffmann | 1 | -0/+4 |
2020-09-17 | acpi: ged: add control regs | Gerd Hoffmann | 1 | -0/+12 |
2020-09-16 | util: introduce qemu_open and qemu_create with error reporting | Daniel P. Berrangé | 1 | -0/+6 |
2020-09-16 | util: rename qemu_open() to qemu_open_old() | Daniel P. Berrangé | 1 | -1/+1 |
2020-09-16 | monitor: simplify functions for getting a dup'd fdset entry | Daniel P. Berrangé | 2 | -2/+2 |
2020-09-16 | osdep: file locking functions are not available on Win32 | Yonggang Luo | 1 | -1/+1 |
2020-09-16 | rcu: Implement drain_call_rcu | Maxim Levitsky | 1 | -0/+1 |
2020-09-15 | virtio-gpu: make virtio_gpu_ops static | Gerd Hoffmann | 1 | -2/+1 |
2020-09-14 | hw/arm/npcm7xx: add board setup stub for CPU and UART clocks | Havard Skinnemoen | 1 | -0/+1 |
2020-09-14 | hw/ssi: NPCM7xx Flash Interface Unit device model | Havard Skinnemoen | 2 | -0/+75 |
2020-09-14 | hw/mem: Stubbed out NPCM7xx Memory Controller model | Havard Skinnemoen | 2 | -0/+38 |
2020-09-14 | hw/nvram: NPCM7xx OTP device model | Havard Skinnemoen | 2 | -0/+82 |
2020-09-14 | hw/arm: Add two NPCM7xx-based machines | Havard Skinnemoen | 1 | -0/+19 |
2020-09-14 | hw/arm: Add NPCM730 and NPCM750 SoC models | Havard Skinnemoen | 1 | -0/+85 |
2020-09-14 | hw/timer: Add NPCM7xx Timer device model | Havard Skinnemoen | 1 | -0/+78 |
2020-09-14 | hw/misc: Add NPCM7xx Clock Controller device model | Havard Skinnemoen | 1 | -0/+48 |
2020-09-14 | hw/misc: Add NPCM7xx System Global Control Registers device model | Havard Skinnemoen | 1 | -0/+43 |
2020-09-13 | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200... | Peter Maydell | 17 | -86/+319 |
2020-09-12 | Merge remote-tracking branch 'remotes/berrange-gitlab/tags/crypt-perf-pull-re... | Peter Maydell | 2 | -6/+2 |
2020-09-12 | Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-5.2-pul... | Peter Maydell | 1 | -1/+2 |
2020-09-11 | util/hexdump: Reorder qemu_hexdump() arguments | Philippe Mathieu-Daudé | 1 | -2/+2 |
2020-09-11 | util/hexdump: Convert to take a void pointer argument | Philippe Mathieu-Daudé | 1 | -1/+2 |
2020-09-11 | Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request... | Peter Maydell | 383 | -2331/+2932 |
2020-09-11 | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging | Peter Maydell | 2 | -36/+61 |
2020-09-10 | crypto/builtin: Move AES_cbc_encrypt into cipher-builtin.inc.c | Richard Henderson | 1 | -4/+0 |
2020-09-10 | crypto: Allocate QCryptoCipher with the subclass | Richard Henderson | 1 | -1/+0 |
2020-09-10 | crypto: Use the correct const type for driver | Richard Henderson | 1 | -1/+1 |
2020-09-10 | crypto: Move QCryptoCipherDriver typedef to crypto/cipher.h | Richard Henderson | 1 | -0/+1 |
2020-09-09 | hw/riscv: Move sifive_test model to hw/misc | Bin Meng | 1 | -0/+0 |
2020-09-09 | hw/riscv: Move sifive_uart model to hw/char | Bin Meng | 1 | -0/+0 |
2020-09-09 | hw/riscv: Move riscv_htif model to hw/char | Bin Meng | 1 | -0/+0 |
2020-09-09 | hw/riscv: Move sifive_plic model to hw/intc | Bin Meng | 1 | -81/+0 |
2020-09-09 | hw/riscv: Move sifive_clint model to hw/intc | Bin Meng | 1 | -0/+0 |
2020-09-09 | hw/riscv: Move sifive_gpio model to hw/gpio | Bin Meng | 3 | -2/+2 |
2020-09-09 | hw/riscv: Move sifive_u_otp model to hw/misc | Bin Meng | 2 | -1/+1 |
2020-09-09 | hw/riscv: Move sifive_u_prci model to hw/misc | Bin Meng | 2 | -1/+1 |
2020-09-09 | hw/riscv: Move sifive_e_prci model to hw/misc | Bin Meng | 1 | -0/+0 |
2020-09-09 | hw/riscv: sifive_u: Connect a DMA controller | Bin Meng | 1 | -0/+11 |
2020-09-09 | hw/riscv: clint: Avoid using hard-coded timebase frequency | Bin Meng | 1 | -1/+3 |
2020-09-09 | hw/riscv: microchip_pfsoc: Hook GPIO controllers | Bin Meng | 1 | -0/+3 |
2020-09-09 | hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs | Bin Meng | 1 | -0/+7 |
2020-09-09 | hw/net: cadence_gem: Add a new 'phy-addr' property | Bin Meng | 1 | -0/+2 |
2020-09-09 | hw/riscv: microchip_pfsoc: Connect a DMA controller | Bin Meng | 1 | -0/+11 |
2020-09-09 | hw/dma: Add SiFive platform DMA controller emulation | Bin Meng | 1 | -0/+57 |
2020-09-09 | hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card | Bin Meng | 1 | -0/+4 |
2020-09-09 | hw/sd: Add Cadence SDHCI emulation | Bin Meng | 1 | -0/+47 |
2020-09-09 | hw/riscv: microchip_pfsoc: Connect 5 MMUARTs | Bin Meng | 1 | -0/+20 |
2020-09-09 | hw/char: Add Microchip PolarFire SoC MMUART emulation | Bin Meng | 1 | -0/+61 |