aboutsummaryrefslogtreecommitdiff
path: root/include
AgeCommit message (Collapse)AuthorFilesLines
2016-06-29vnc: generalize "VNC server running on ..." messagePaolo Bonzini1-7/+0
The message is useful whenever the user specifies "-vnc to=XX". Move it to ui/vnc.c. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29scsi: esp: fix migrationPaolo Bonzini1-1/+4
Commit 926cde5 ("scsi: esp: make cmdbuf big enough for maximum CDB size", 2016-06-16) changed the size of a migrated field. Split it in two parts, and only migrate the second part in a new vmstate version. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29isa: introduce wrapper isa_connect_gpio_outEfimov Vasily1-0/+1
Currently a direct access to the device structure field is used to connect ISA device IRQ to the bus. GPIO access should be used instead if possible. The patch adds wrapper isa_connect_gpio_out. The function connects specified output GPIO to specified ISA IRQ. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29ICH9 LPC: handle GSI as qdev GPIOEfimov Vasily1-1/+3
The ICH9 LPC bridge has 24 output IRQs connected to GSI. Currently the IRQs are referenced by pointers. The pointers are initialized at startup by direct access to the structure fields. This violates Qemu device model. The patch makes the IRQs handling to use GPIO model. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29ich9: unify pic and ioapic IRQ vectorsPaolo Bonzini1-2/+1
ich9->pic and ich9->ioapic differ for the first 16 GSIs (because ich9->pic is wired to 8259+IOAPIC but ich9->ioapic is wired to IOAPIC only). However, ich9->ioapic is never used for the first 16 GSIs, so the two vectors can be merged. Reviewed-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29ICH9 SMB: make TYPE_ICH9_SMB_DEVICE macro publicEfimov Vasily1-0/+2
ICH9 SMB bridge can be created using qdev API despite existence of helper function. The type name is needed for such creation. Using a preprocessor alias instead the string type name itself is preferable. The patch makes the alias accessible through the header. Signed-off-by: Efimov Vasily <real@ispras.ru> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29port92: handle A20 IRQ as GPIOEfimov Vasily1-0/+2
The port92 device has outgouing IRQ line A20. Currently the IRQ is referenced by a pointer which normally is set during machine initialization. The pointer is never changed at runtime. Hence, common GPIO model can be applied to A20 IRQ line. Note that checking for IRQ to be connected as in previous version of code is not required qemu_set_irq will do it. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29pckbd: handle A20 IRQ as GPIOEfimov Vasily1-0/+1
The i8042 device has outgouing IRQ line A20. Currently the IRQ is referenced by a pointer which normally is set during machine initialization. The pointer is never changed at runtime. So common GPIO model can be applied to A20 IRQ line. Note that checking for IRQ to be connected as in previous version of code is not required because qemu_set_irq will do it. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29Q35: implement property interfece to several parametersEfimov Vasily2-2/+9
During creation of Q35 instance several parameters are set using direct access. It violates Qemu device model. Correctly, the parameters should be handled as object properties. The patch adds four link type properties for fields: mch.ram_memory mch.pci_address_space mch.system_memory mch.address_space_io And, it adds two size type properties for fields: mch.below_4g_mem_size mch.above_4g_mem_size Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29pflash: make TYPE_CFI_PFLASH0{1,2} macros publicEfimov Vasily1-0/+3
qdev API can be used to create CFI pflash devices despite existance of helper functions. The type name is needed in course of such creation. Using the preprocessor alias instead of the string literal itself is preferable. The patch makes the aliases accessible through the header. Signed-off-by: Efimov Vasily <real@ispras.ru> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29vmport: identify vmport type by macro TYPE_VMPORTEfimov Vasily1-1/+2
Currently vmport device is identified by the string literal. Using a preprocessor alias instead is preferable. Signed-off-by: Efimov Vasily <real@ispras.ru> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29pcspk: convert "pit" property type from ptr to linkEfimov Vasily1-1/+1
The speaker device needs pointer to ISA PIT device to operate. But according to qdev-properties.h, properties of pointer type should be avoided. It seems a link type property is a good substitution. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-29ide: move headers to include folderEfimov Vasily3-0/+1116
The patch moves "hw/ide/achi.h", "hw/ide/pci.h" and "hw/ide/internal.h" headers to corresponding folders inside "include" folder alike other Qemu headers. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-24pc: acpi: drop intermediate PCMachineState.node_cpuIgor Mammedov1-1/+0
PCMachineState.node_cpu was used for mapping APIC ID to numa node id as CPU entries in SRAT used to be built on sparse APIC ID bitmap (up to apic_id_limit). However since commit 5803fce pc: acpi: SRAT: create only valid processor lapic entries CPU entries in SRAT aren't build using apic bitmap but using 0..maxcpus index instead which is also used for creating numa_info[x].node_cpu map. So instead of doing useless intermediate conversion from 1. node by cpu index -> node by apic id i.e. numa_info[x].node_cpu -> PCMachineState.node_cpu 2. apic id -> srat entry PMX PCMachineState.node_cpu[apic id] -> PMX value use numa_info[x].node_cpu map directly like ARM does and do 1. numa_info[x].node_cpu -> PMX value using index in range 0..maxcpus and drop not necessary PCMachineState.node_cpu and related code. That also removes the last (not counting legacy hotplug) dependency of ACPI code on apic_id_limit and need to allocate huge sparse PCMachineState.node_cpu array in case of 32-bit APIC IDs. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24pc: use new CPU hotplug interface since 2.7 machine typeIgor Mammedov3-0/+9
For compatibility reasons PC/Q35 will start with legacy CPU hotplug interface by default but with new CPU hotplug AML code since 2.7 machine type. That way legacy firmware that doesn't use QEMU generated ACPI tables will be able to continue using legacy CPU hotplug interface. While new machine type, with firmware supporting QEMU provided ACPI tables, will generate new CPU hotplug AML, which will switch to new CPU hotplug interface when guest OS executes its _INI method on ACPI tables loading. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: cpuhp: add cpu._OST handlingIgor Mammedov1-0/+4
it adds HW and AML parts for CPU_Device._OST method handling to allow OSPM reports status of hot-(un)plug operation. And extends QMP command query-acpi-ospm-status to report CPU's OST info along with already reported PC-DIMM devices. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: cpuhp: implement hot-remove parts of CPU hotplug interfaceIgor Mammedov1-0/+8
it adds hw registers needed for handling CPU hot-remove and corresponding AML methods to request and eject a CPU with necessary hotplug callbacks in pc,piix4,ich9 code. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: cpuhp: implement hot-add parts of CPU hotplug interfaceIgor Mammedov1-1/+4
it adds hw registers needed for handling CPU hot-add and corresponding AML methods to handle hot-add events on guest side. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24pc: acpi: introduce AcpiDeviceIfClass.madt_cpu hookIgor Mammedov2-0/+12
Add madt_cpu callback to AcpiDeviceIfClass and use it for generating LAPIC MADT entries for CPUs. Later it will be used for generating x2APIC entries in case of more than 255 CPUs and also would be reused by ARM target when ACPI CPU hotplug is introduced there. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: cpuhp: add CPU devices AML with _STA methodIgor Mammedov2-0/+53
it adds CPU objects to DSDT with _STA method and QEMU side of CPU hotplug interface initialization with registers sufficient to handle _STA requests, including necessary hotplug callbacks in piix4,ich9 code. Hot-(un)plug hw/acpi parts will be added by corresponding follow up patches. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24pc: piix4/ich9: add 'cpu-hotplug-legacy' propertyIgor Mammedov1-0/+1
It will be used to select which hotplug call-back is called and for switching from legacy mode into new one. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: add aml_call5Xiao Guangrong1-0/+2
It will be used by NVDIMM ACPI Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: add aml_object_typeXiao Guangrong1-0/+1
Implement ObjectType which is used by NVDIMM _DSM method in later patch Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24nvdimm: support nvdimm labelXiao Guangrong1-1/+54
Introduce a parameter, 'label-size', which is the size of nvdimm label data area which is reserved at the end of backend memory. It is required at least 128k Two callbacks, read_label_data() and write_label_data(), are used to operate the label area Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24pc-dimm: introduce get_vmstate_memory_region callbackXiao Guangrong1-1/+4
This callback returns the MemoryRegion that is the memory of dimm should be kept during live migration nvdimm device is different with pc-dimm as its memory includes not only the MemoryRegion directly mapping to guest's address space but also the memory used as label data Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi: Add IPMI table entriesCorey Minyard1-0/+22
Use the ACPI table construction tools to create an ACPI entry for IPMI. This adds a function called build_acpi_ipmi_devices to add an DSDT entry for IPMI if IPMI is compiled in and an IPMI device exists. It also adds a dummy function if IPMI is not compiled in. This conforms to section "C3-2 Locating IPMI System Interfaces in ACPI Name Space" in the IPMI 2.0 specification. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24ipmi: Add SMBIOS table entryCorey Minyard1-0/+15
Add an IPMI table entry to the SMBIOS. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-23Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160623' ↵Peter Maydell1-4/+15
into staging ppc patch queue for 2016-06-23 Currently outstanding patches for spapr, target-ppc and related devices. This batch has: * Significant new progress towards full support for hypervisor mode * Assorted bugfixes * Some preliminary patches towards dynamic DMA window support The last involves a change to memory.c, which Paolo has said I can take through this tree. # gpg: Signature made Thu 23 Jun 2016 06:47:53 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.7-20160623: ppc: Disable huge page support if it is not available for main RAM ppc: Add P7/P8 Power Management instructions ppc: Move exception generation code out of line ppc: Turn a bunch of booleans from int to bool ppc: Add real mode CI load/store instructions for P7 and P8 ppc: Rework generation of priv and inval interrupts ppc: Fix generation if ISI/DSI vs. HV mode ppc: Fix POWER7 and POWER8 exception definitions ppc: fix exception model for HV mode ppc: define a default LPCR value ppc: Fix rfi/rfid/hrfi/... emulation memory: Add reporting of supported page sizes ppc: Improve emulation of THRM registers target-ppc: Fix rlwimi, rlwinm, rlwnm again ppc64: disable gen_pause() for linux-user mode tests: Use '+=' to add additional tests, not '=' powerpc/mm: Update the WIMG check during H_ENTER Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-22usb: Add QOM property "attached".Gerd Hoffmann1-0/+1
USB devices in attached state are visible to the guest. This patch adds a QOM property for this. Write access is opt-in per device. Some devices manage attached state automatically (usb-host, usb-serial, usb-redir), so we can't enable write access universally but have to do it on a case by case base. So far, no device opts in. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: 1465984019-28963-4-git-send-email-kraxel@redhat.com [ minor codestyle fix ] Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-06-22usb: make USBDevice->attached boolGerd Hoffmann1-1/+1
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: 1465984019-28963-3-git-send-email-kraxel@redhat.com
2016-06-22memory: Add reporting of supported page sizesAlexey Kardashevskiy1-4/+15
Every IOMMU has some granularity which MemoryRegionIOMMUOps::translate uses when translating, however this information is not available outside the translate context for various checks. This adds a get_min_page_size callback to MemoryRegionIOMMUOps and a wrapper for it so IOMMU users (such as VFIO) can know the minimum actual page size supported by an IOMMU. As IOMMU MR represents a guest IOMMU, this uses TARGET_PAGE_SIZE as fallback. This removes vfio_container_granularity() and uses new helper in memory_region_iommu_replay() when replaying IOMMU mappings on added IOMMU memory region. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Alex Williamson <alex.williamson@redhat.com> [dwg: Removed an unnecessary calculation] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-20Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' ↵Peter Maydell2-0/+47
into staging # gpg: Signature made Mon 20 Jun 2016 21:29:27 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/tracing-pull-request: (42 commits) trace: split out trace events for linux-user/ directory trace: split out trace events for qom/ directory trace: split out trace events for target-ppc/ directory trace: split out trace events for target-s390x/ directory trace: split out trace events for target-sparc/ directory trace: split out trace events for net/ directory trace: split out trace events for audio/ directory trace: split out trace events for ui/ directory trace: split out trace events for hw/alpha/ directory trace: split out trace events for hw/arm/ directory trace: split out trace events for hw/acpi/ directory trace: split out trace events for hw/vfio/ directory trace: split out trace events for hw/s390x/ directory trace: split out trace events for hw/pci/ directory trace: split out trace events for hw/ppc/ directory trace: split out trace events for hw/9pfs/ directory trace: split out trace events for hw/i386/ directory trace: split out trace events for hw/isa/ directory trace: split out trace events for hw/sd/ directory trace: split out trace events for hw/sparc/ directory ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-20trace: [all] Add "guest_mem_before" eventLluís Vilanova2-0/+47
The event is described in "trace-events". Note that the "MO_AMASK" flag is not traced, since it does not seem to affect the visible semantics of instructions. [s/inline inline/inline/ to fix clang build. --Stefan] Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 146549350711.18437.726780393247474362.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2016-06-20' ↵Peter Maydell1-2/+2
into staging Error reporting patches for 2016-06-20 # gpg: Signature made Mon 20 Jun 2016 15:56:15 BST # gpg: using RSA key 0x3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-error-2016-06-20: log: Fix qemu_set_log_filename() error handling log: Fix qemu_set_dfilter_ranges() error reporting log: Plug memory leak on multiple -dfilter coccinelle: Remove unnecessary variables for function return value error: Remove unnecessary local_err variables error: Remove NULL checks on error_propagate() calls vl: Error messages need to go to stderr, fix some Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-20log: Fix qemu_set_log_filename() error handlingMarkus Armbruster1-1/+1
When qemu_set_log_filename() detects an invalid file name, it reports an error, closes the log file (if any), and starts logging to stderr (unless daemonized or nothing is being logged). This is wrong. Asking for an invalid log file on the command line should be fatal. Asking for one in the monitor should fail without messing up an existing logfile. Fix by converting qemu_set_log_filename() to Error. Pass it &error_fatal, except for hmp_logfile report errors. This also permits testing without a subprocess, so do that. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <1466011636-6112-4-git-send-email-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-06-20log: Fix qemu_set_dfilter_ranges() error reportingMarkus Armbruster1-1/+1
g_error() is not an acceptable way to report errors to the user: $ qemu-system-x86_64 -dfilter 1000+0 ** (process:17187): ERROR **: Failed to parse range in: 1000+0 Trace/breakpoint trap (core dumped) g_assert() isn't, either: $ qemu-system-x86_64 -dfilter 1000x+64 ** ERROR:/work/armbru/qemu/util/log.c:180:qemu_set_dfilter_ranges: assertion failed: (e == range_op) Aborted (core dumped) Convert qemu_set_dfilter_ranges() to Error. Rework its deeply nested control flow. Touch up the error messages. Call it with &error_fatal. This also permits testing without a subprocess, so do that. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <1466011636-6112-3-git-send-email-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-06-20blockjob: add AioContext attached callbackStefan Hajnoczi1-0/+7
Block jobs that use additional BDSes or event loop resources need a callback to get their affairs in order when the AioContext is switched. Simple block jobs don't need an attach callback, they automatically work thanks to the generic attach/detach notifiers that this patch adds. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Message-id: 1466096189-6477-7-git-send-email-stefanha@redhat.com
2016-06-20block: use safe iteration over AioContext notifiersStefan Hajnoczi1-0/+2
It's possible that an AioContext notifier user was close to finishing when .detach_aio_context() or .attached_aio_context() is called. In that case they may call bdrv_remove_aio_context_notifier() during the callback. Use safe iteration to avoid crashing when the notifier list is modified during iteration. We must not only handle the case where the current aio notifier is removed during a callback but also the one where any other aio notifier is removed. The next patch adds an AioContext notifier for block jobs and they really could be terminating just as .detach_aio_context() is invoked. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Message-id: 1466096189-6477-6-git-send-email-stefanha@redhat.com
2016-06-20blockjob: add pause pointsStefan Hajnoczi1-3/+32
Block jobs are coroutines that usually perform I/O but sometimes also sleep or yield. Currently only sleeping or yielded block jobs can be paused. This means jobs that do not sleep or yield (using block_job_yield()) are unaffected by block_job_pause(). Add block_job_pause_point() so that block jobs can mark quiescent points that are suitable for pausing. This solves the problem that it can take a block job a long time to pause if it is performing a long series of I/O operations. Transitioning to paused state involves a .pause()/.resume() callback. These callbacks are used to ensure that I/O and event loop activity has ceased while the job is at a pause point. Note that this patch introduces a stricter pause state than previously. The job->busy flag was incorrectly documented as a quiescent state without I/O pending. This is violated by any job that has I/O pending across sleep or block_job_yield(), like the mirror block job. [Add missing block_job_should_pause() check to avoid deadlock after job->driver->pause() in block_job_pause_point(). --Stefan] Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Message-id: 1466096189-6477-4-git-send-email-stefanha@redhat.com
2016-06-20blockjob: rename block_job_is_paused()Stefan Hajnoczi1-9/+0
The block_job_is_paused() function name is not great because callers only use it to determine whether pausing has been requested. Rename it to highlight those semantics and remove it from the public header file as there are no external callers. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Message-id: 1466096189-6477-3-git-send-email-stefanha@redhat.com
2016-06-17Merge remote-tracking branch ↵Peter Maydell6-9/+361
'remotes/pmaydell/tags/pull-target-arm-20160617' into staging target-arm queue: * GICv3 emulation # gpg: Signature made Fri 17 Jun 2016 15:24:28 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20160617: (22 commits) ACPI: ARM: Present GIC version in MADT table hw/timer: Add value matching support to aspeed_timer target-arm/monitor.c: Advertise emulated GICv3 in capabilities target-arm/machine.c: Allow user to request GICv3 emulation hw/intc/arm_gicv3: Add IRQ handling CPU interface registers hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers hw/intc/arm_gicv3: Implement gicv3_cpuif_update() hw/intc/arm_gicv3: Implement GICv3 CPU interface registers hw/intc/arm_gicv3: Implement gicv3_set_irq() hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions hw/intc/arm_gicv3: Implement GICv3 redistributor registers hw/intc/arm_gicv3: Implement GICv3 distributor registers hw/intc/arm_gicv3: Implement functions to identify next pending irq hw/intc/arm_gicv3: ARM GICv3 device framework hw/intc/arm_gicv3: Add vmstate descriptors hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure hw/intc/arm_gicv3: Add state information target-arm: Add mp-affinity property for ARM CPU class target-arm: Provide hook to tell GICv3 about changes of security state target-arm: Define new arm_is_el3_or_mon() function ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-17ACPI: ARM: Present GIC version in MADT tableShannon Zhao1-1/+3
In ACPI 5.1 Errata, it adds GIC version in GIC distributor structure. This is useful for guest kernel to identify which version GIC hardware is. Update GIC distributor structure and present GIC version in MADT table. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1465960955-17388-1-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-17hw/timer: Add value matching support to aspeed_timerAndrew Jeffery1-2/+3
Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the palmetto-bmc machine. Two match registers are provided for each timer. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1465974248-20434-1-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-17hw/intc/arm_gicv3: Implement functions to identify next pending irqPeter Maydell1-0/+18
Implement the GICv3 logic to recalculate the highest priority pending interrupt for each CPU after some part of the GIC state has changed. We avoid unnecessary full recalculation where possible. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-11-git-send-email-peter.maydell@linaro.org
2016-06-17hw/intc/arm_gicv3: ARM GICv3 device frameworkShlomo Pongratz1-0/+32
This patch includes the device class itself, some ID register value functions which will be needed by both distributor and redistributor, and some skeleton functions for handling interrupts coming in and going out, which will be filled in in a subsequent patch. Signed-off-by: Shlomo Pongratz <shlomo.pongratz@huawei.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-10-git-send-email-peter.maydell@linaro.org [PMM: pulled this patch earlier in the sequence, and left some code out of it for a later patch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
2016-06-17hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structurePeter Maydell1-3/+2
Move the GICv3 parent_irq and parent_fiq pointers into the GICv3CPUState structure rather than giving them their own array. This will make it easy to assert the IRQ and FIQ lines for a particular CPU interface without having to know or calculate the CPU index for the GICv3CPUState we are working on. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-8-git-send-email-peter.maydell@linaro.org
2016-06-17hw/intc/arm_gicv3: Add state informationPavel Fedin1-3/+189
Add state information to GICv3 object structure and implement arm_gicv3_common_reset(). This commit includes accessor functions for the fields which are stored as bitmaps in uint32_t arrays. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-7-git-send-email-peter.maydell@linaro.org [PMM: significantly overhauled: * Add missing qom/cpu.h include * Remove legacy-only state fields (we can add them later if/when we add legacy emulation) * Use arrays of uint32_t to store the various distributor bitmaps, and provide accessor functions for the various set/test/etc operations * Add various missing register offset #defines * Accessor macros which combine distributor and redistributor behaviour removed * Fields in state structures renamed to match architectural register names * Corrected the reset value for GICR_IENABLER0 since we don't support legacy mode * Added ARM_LINUX_BOOT_IF interface for "we are directly booting a kernel in non-secure" so that we can fake up the firmware-mandated reconfiguration only when we need it ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
2016-06-17bitops.h: Implement half-shuffle and half-unshuffle opsPeter Maydell1-0/+108
A half-shuffle operation takes a word with zeros in the high half: 0000 0000 0000 0000 ABCD EFGH IJKL MNOP and spreads the bits out so they are in every other bit of the word: 0A0B 0C0D 0E0F 0G0H 0I0J 0K0L 0M0N 0O0P A half-unshuffle performs the reverse operation. Provide functions in bitops.h which implement these operations for 32-bit and 64-bit inputs, and add tests for them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-3-git-send-email-peter.maydell@linaro.org
2016-06-17migration: Define VMSTATE_UINT64_2DARRAYPeter Maydell1-0/+6
Define a VMSTATE_UINT64_2DARRAY macro, to go with the ones we already have for other type sizes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-2-git-send-email-peter.maydell@linaro.org
2016-06-17qdev: Use GList for global propertiesEduardo Habkost1-1/+0
If the same GlobalProperty struct is registered twice, the list entry gets corrupted, making tqe_next points to itself, and qdev_prop_set_globals() gets stuck in a loop. The bug can be easily reproduced by running: $ qemu-system-x86_64 -rtc-td-hack -rtc-td-hack Change global_props to use GList instead of queue.h, making the code simpler and able to deal with properties being registered twice. Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
generated by cgit v1.1 at 2024-12-27 20:06:30 +0000