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2023-01-05tcg: Introduce tcg_type_sizeRichard Henderson1-0/+16
Add a helper function for computing the size of a type. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Move TCG_TYPE_COUNT outside enumRichard Henderson1-1/+2
The count is not itself an enumerator. Move it outside to prevent the compiler from considering it with -Wswitch-enum. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Add temp_subindex to TCGTempRichard Henderson1-0/+1
Record the location of a TCGTemp within a larger object. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Move TCG_{LOW,HIGH} to tcg-internal.hRichard Henderson2-40/+5
Move the error-generating fallback from tcg-op.c, and replace "_link_error" with modern QEMU_ERROR markup. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Introduce paired register allocationRichard Henderson1-0/+2
There are several instances where we need to be able to allocate a pair of registers to related inputs/outputs. Add 'p' and 'm' register constraints for this, in order to be able to allocate the even/odd register first or second. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04qemu/main-loop: Introduce QEMU_IOTHREAD_LOCK_GUARDRichard Henderson1-0/+29
Create a wrapper for locking/unlocking the iothread lock. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-12-23qemu/xattr.h: Exclude <sys/xattr.h> for WindowsBin Meng1-1/+3
Windows does not have <sys/xattr.h>. Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20221219102022.2167736-2-bin.meng@windriver.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-21Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into stagingPeter Maydell3-2/+4
ppc patch queue for 2022-12-21: This queue contains a MAINTAINERS update, the implementation of the Freescale eSDHC, the introduction of the DEXCR/HDEXCR instructions and other assorted fixes (most of them for the e500 board). # gpg: Signature made Wed 21 Dec 2022 17:18:53 GMT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu: target/ppc: Check DEXCR on hash{st, chk} instructions target/ppc: Implement the DEXCR and HDEXCR hw/ppc/e500: Move comment to more appropriate place hw/ppc/e500: Resolve variable shadowing hw/ppc/e500: Prefer local variable over qdev_get_machine() hw/ppc/virtex_ml507: Prefer local over global variable target/ppc/mmu_common: Fix table layout of "info tlb" HMP command target/ppc/mmu_common: Log which effective address had no TLB entry found hw/ppc/spapr: Reduce "vof.h" inclusion hw/ppc/vof: Do not include the full "cpu.h" target/ppc/kvm: Add missing "cpu.h" and "exec/hwaddr.h" hw/ppc/e500: Add Freescale eSDHC to e500plat hw/sd/sdhci: Support big endian SD host controller interfaces MAINTAINERS: downgrade PPC KVM/TCG CPUs and pSeries to 'Odd Fixes' Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-21hw/ppc/spapr: Reduce "vof.h" inclusionPhilippe Mathieu-Daudé1-1/+2
Currently objects including "hw/ppc/spapr.h" are forced to be target specific due to the inclusion of "vof.h" in "spapr.h". "spapr.h" only uses a Vof pointer, so doesn't require the structure declaration. The only place where Vof structure is accessed is in spapr.c, so include "vof.h" there, and forward declare the structure in "spapr.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20221213123550.39302-4-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21hw/ppc/vof: Do not include the full "cpu.h"Philippe Mathieu-Daudé1-1/+1
"vof.h" doesn't need the full "cpu.h" to get the target_ulong definition, including "exec/cpu-defs.h" is enough. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20221213123550.39302-3-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21hw/sd/sdhci: Support big endian SD host controller interfacesPhilippe Mathieu-Daudé1-0/+1
Some SDHCI IP can be synthetized in various endianness: https://github.com/u-boot/u-boot/blob/v2021.04/doc/README.fsl-esdhc - CONFIG_SYS_FSL_ESDHC_BE ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined by ESDHC IP's endian mode or processor's endian mode. Our current implementation is little-endian. In order to support big endianness: - Rename current MemoryRegionOps as sdhci_mmio_le_ops ('le') - Add an 'endianness' property to SDHCIState (default little endian) - Set the 'io_ops' field in realize() after checking the property - Add the sdhci_mmio_be_ops (big-endian) MemoryRegionOps. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20221101222934.52444-3-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Peter Maydell12-19/+111
into staging virtio,pc,pci: features, cleanups, fixes make TCO watchdog work by default part of generic vdpa support asid interrupt for vhost-vdpa added flex bus port DVSEC for cxl misc fixes, cleanups, documentation Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed 21 Dec 2022 12:32:36 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (41 commits) contrib/vhost-user-blk: Replace lseek64 with lseek libvhost-user: Switch to unsigned int for inuse field in struct VuVirtq hw/virtio: Extract QMP related code virtio-qmp.c hw/virtio: Extract config read/write accessors to virtio-config-io.c hw/virtio: Constify qmp_virtio_feature_map_t[] hw/virtio: Guard and restrict scope of qmp_virtio_feature_map_t[] hw/virtio: Rename virtio_ss[] -> specific_virtio_ss[] hw/virtio: Add missing "hw/core/cpu.h" include hw/cxl/device: Add Flex Bus Port DVSEC hw/acpi: Rename tco.c -> ich9_tco.c acpi/tests/avocado/bits: add mformat as one of the dependencies docs/acpi/bits: document BITS_DEBUG environment variable pci: drop redundant PCIDeviceClass::is_bridge field remove DEC 21154 PCI bridge vhost: fix vq dirty bitmap syncing when vIOMMU is enabled acpi/tests/avocado/bits: add SPDX license identifiers for bios bits tests include/hw: attempt to document VirtIO feature variables vhost-user: send set log base message only once vdpa: always start CVQ in SVQ mode if possible vdpa: add shadow_data to vhost_vdpa ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-21hw/acpi: Rename tco.c -> ich9_tco.cPhilippe Mathieu-Daudé2-2/+2
tco.c contains the ICH9 implementation of its "total cost of ownership". Rename it accordingly to emphasis this is a part of the ICH9 model. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221212105115.2113-1-philmd@linaro.org> Acked-by: Igor Mammedov <imammedo@redhat.com>
2022-12-21pci: drop redundant PCIDeviceClass::is_bridge fieldIgor Mammedov2-9/+2
and use cast to TYPE_PCI_BRIDGE instead. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221129101341.185621-3-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org>
2022-12-21remove DEC 21154 PCI bridgeIgor Mammedov1-1/+0
Code has not been used practically since its inception (2004) f2aa58c6f4a20 UniNorth PCI bridge support or maybe even earlier, but it was consuming contributors time as QEMU was being rewritten. Drop it for now. Whomever would like to actually use the thing, can make sure it actually works/reintroduce it back when there is a user. PS: I've stumbled upon this when replacing PCIDeviceClass::is_bridge field with QOM cast to PCI_BRIDGE type. Unused DEC 21154 was the only one trying to use the field with plain PCIDevice. It's not worth keeping the field around for the sake of the code that was commented out 'forever'. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20221129101341.185621-2-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-12-21include/hw: attempt to document VirtIO feature variablesAlex Bennée2-4/+40
We have a bunch of variables associated with the device and the vhost backend which are used inconsistently throughout the code base. Lets start trying to bring some order by agreeing what each variable is for. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Stefano Garzarella <sgarzare@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Stefan Hajnoczi <stefanha@gmail.com> Message-Id: <20221123152134.179929-2-alex.bennee@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-12-21vdpa: add shadow_data to vhost_vdpaEugenio Pérez1-0/+2
The memory listener that thells the device how to convert GPA to qemu's va is registered against CVQ vhost_vdpa. memory listener translations are always ASID 0, CVQ ones are ASID 1 if supported. Let's tell the listener if it needs to register them on iova tree or not. Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20221215113144.322011-12-eperezma@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-12-21vdpa: add asid parameter to vhost_vdpa_dma_map/unmapEugenio Pérez1-3/+11
So the caller can choose which ASID is destined. No need to update the batch functions as they will always be called from memory listener updates at the moment. Memory listener updates will always update ASID 0, as it's the passthrough ASID. All vhost devices's ASID are 0 at this moment. Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20221215113144.322011-10-eperezma@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-12-21vdpa: add vdpa-dev supportLongpeng1-0/+43
Supports vdpa-dev, we can use the deivce directly: -M microvm -m 512m -smp 2 -kernel ... -initrd ... -device \ vhost-vdpa-device,vhostdev=/dev/vhost-vdpa-x Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Longpeng <longpeng2@huawei.com> Message-Id: <20221215134944.2809-3-longpeng2@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-12-21virtio: get class_id and pci device id by the virtio idLongpeng1-0/+5
Add helpers to get the "Transitional PCI Device ID" and "class_id" of the device specified by the "Virtio Device ID". These helpers will be used to build the generic vDPA device later. Acked-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Longpeng <longpeng2@huawei.com> Message-Id: <20221215134944.2809-2-longpeng2@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-12-21hw: Add compat machines for 8.0Cornelia Huck2-0/+6
Add 8.0 machine types for arm/i440fx/m68k/q35/s390x/spapr. Reviewed-by: Cédric Le Goater <clg@kaod.org> [ppc] Reviewed-by: Thomas Huth <thuth@redhat.com> [s390x] Reviewed-by: Greg Kurz <groug@kaod.org> [ppc] Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20221212152145.124317-2-cohuck@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2022-12-20accel/tcg: Move remainder of page locking to tb-maint.cRichard Henderson1-6/+0
The only thing that still touches PageDesc in translate-all.c are some locking routines related to tb-maint.c which have not yet been moved. Do so now. Move some code up in tb-maint.c as well, to untangle the maze of ifdefs, and allow a sensible final ordering. Move some declarations from exec/translate-all.h to internal.h, as they are only used within accel/tcg/. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-12-20accel/tcg: Use interval tree for TBs in user-only modeRichard Henderson1-3/+40
Begin weaning user-only away from PageDesc. Since, for user-only, all TB (and page) manipulation is done with a single mutex, and there is no virtual/physical discontinuity to split a TB across discontinuous pages, place all of the TBs into a single IntervalTree. This makes it trivial to find all of the TBs intersecting a range. Retain the existing PageDesc + linked list implementation for system mode. Move the portion of the implementation that overlaps the new user-only code behind the common ifdef. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-12-20util: Add interval-tree.cRichard Henderson1-0/+99
Copy and simplify the Linux kernel's interval_tree_generic.h, instantiating for uint64_t. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-12-19pci: Move HMP command from hw/pci/pcie_aer.c to pci-hmp-cmds.cMarkus Armbruster2-3/+1
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221201121133.3813857-10-armbru@redhat.com>
2022-12-18Merge tag 'pull-loongarch-20221215' of https://gitlab.com/gaosong/qemu into ↵Peter Maydell1-0/+5
staging Add cfi01 pflash device # gpg: Signature made Thu 15 Dec 2022 07:49:03 GMT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20221215' of https://gitlab.com/gaosong/qemu: hw/loongarch/virt: Add cfi01 pflash device Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-17Merge tag 'pull-target-arm-20221216' of ↵Peter Maydell5-39/+4
https://git.linaro.org/people/pmaydell/qemu-arm into staging reset refactoring queue: * remove uses of qdev_reset_all(), qbus_reset_all(), device_legacy_reset() * convert various devices to 3-phase reset, so we can remove their uses of device_class_set_parent_reset() # gpg: Signature made Fri 16 Dec 2022 21:41:11 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20221216' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/pci-host/pnv_phb3_msi: Convert TYPE_PHB3_MSI to 3-phase reset hw/intc/xics: Convert TYPE_ICS to 3-phase reset hw/intc/xics: Reset TYPE_ICS objects with device_cold_reset() pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase reset pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase reset hw/display/virtio-vga: Convert TYPE_VIRTIO_VGA_BASE to 3-phase reset hw/virtio: Convert TYPE_VIRTIO_PCI to 3-phase reset target/xtensa: Convert to 3-phase reset target/tricore: Convert to 3-phase reset target/sparc: Convert to 3-phase reset target/sh4: Convert to 3-phase reset target/rx: Convert to 3-phase reset target/riscv: Convert to 3-phase reset target/ppc: Convert to 3-phase reset target/openrisc: Convert to 3-phase reset target/nios2: Convert to 3-phase reset target/mips: Convert to 3-phase reset target/microblaze: Convert to 3-phase reset target/m68k: Convert to 3-phase reset target/loongarch: Convert to 3-phase reset ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-16hw/pci-host/pnv_phb3_msi: Convert TYPE_PHB3_MSI to 3-phase resetPeter Maydell1-1/+1
Convert the TYPE_PHB3_MSI class to 3-phase reset, so we can avoid using the device_class_set_parent_reset() function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221125115240.3005559-8-peter.maydell@linaro.org
2022-12-16pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase resetPeter Maydell1-1/+1
Convert the TYPE_CXL_ROOT_PORT and TYPE_PNV_PHB_ROOT_PORT classes to 3-phase reset, so they don't need to use the deprecated device_class_set_parent_reset() function any more. We have to do both in the same commit, because they keep the parent_reset field in their common parent class's class struct. Note that pnv_phb_root_port_class_init() was pointlessly setting dc->reset twice, once by calling device_class_set_parent_reset() and once directly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221125115240.3005559-5-peter.maydell@linaro.org
2022-12-16hw/misc: Convert TYPE_MOS6522 subclasses to 3-phase resetPeter Maydell1-1/+1
Convert the various subclasses of TYPE_MOS6522 to 3-phase reset. This removes some uses of device_class_set_parent_reset(), which we would eventually like to be able to get rid of. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221110143459.3833425-3-peter.maydell@linaro.org
2022-12-16hw/input/ps2.c: Convert TYPE_PS2_{KBD, MOUSE}_DEVICE to 3-phase resetPeter Maydell1-1/+1
Convert the child classes TYPE_PS2_KBD_DEVICE and TYPE_PS2_MOUSE_DEVICE to the 3-phase reset system. This allows us to stop using the old device_class_set_parent_reset() function. We don't need to register an 'exit' phase function for the subclasses, because they have no work to do in that phase. Passing NULL to resettable_class_set_parent_phases() will result in the parent class method being called for that phase, so we don't need to register a function purely to chain to the parent 'exit' phase function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221109170009.3498451-3-peter.maydell@linaro.org
2022-12-16hw: Remove device_legacy_reset()Peter Maydell1-9/+0
The device_legacy_reset() function is now not used anywhere, so we can remove the implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-16qdev: Remove qdev_reset_all() and qbus_reset_all()Peter Maydell1-26/+0
Remove the qdev_reset_all() and qbus_reset_all() functions, now we have moved all the callers over to the new device_cold_reset() and bus_cold_reset() functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-16Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into stagingPeter Maydell13-171/+581
Block layer patches - Code cleanups around block graph modification - Simplify drain - coroutine_fn correctness fixes, including splitting generated coroutine wrappers into co_wrapper (to be called only from non-coroutine context) and co_wrapper_mixed (both coroutine and non-coroutine context) - Introduce a block graph rwlock # gpg: Signature made Thu 15 Dec 2022 15:08:34 GMT # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * tag 'for-upstream' of https://repo.or.cz/qemu/kevin: (50 commits) block: GRAPH_RDLOCK for functions only called by co_wrappers block: use co_wrapper_mixed_bdrv_rdlock in functions taking the rdlock block-coroutine-wrapper.py: introduce annotations that take the graph rdlock Mark assert_bdrv_graph_readable/writable() GRAPH_RD/WRLOCK graph-lock: TSA annotations for lock/unlock functions block: assert that graph read and writes are performed correctly block: remove unnecessary assert_bdrv_graph_writable() block: wrlock in bdrv_replace_child_noperm block: Fix locking in external_snapshot_prepare() test-bdrv-drain: Fix incorrrect drain assumptions clang-tsa: Add macros for shared locks clang-tsa: Add TSA_ASSERT() macro Import clang-tsa.h async: Register/unregister aiocontext in graph lock list graph-lock: Implement guard macros graph-lock: Introduce a lock to protect block graph operations block: Factor out bdrv_drain_all_begin_nopoll() block/dirty-bitmap: convert coroutine-only functions to co_wrapper block: convert bdrv_create to co_wrapper block-coroutine-wrapper.py: support also basic return types ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15Merge tag 'pull-request-2022-12-15' of https://gitlab.com/thuth/qemu into ↵Peter Maydell1-0/+6
staging * s390x PCI fixes and improvements (for the ISM device) * Fix emulated MVCP and MVCS s390x instructions * Clean-ups for the e1000e qtest * Enable qtests on Windows * Update FreeBSD CI to version 12.4 * Check --disable-tcg for ppc64 in the CI * Improve scripts/make-releases a little bit * Many other misc small clean-ups and fixes here and there # gpg: Signature made Thu 15 Dec 2022 15:05:44 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-12-15' of https://gitlab.com/thuth/qemu: (23 commits) tests/qtest/vhost-user-blk-test: don't abort all qtests on missing envar .gitlab/issue_templates: Move suggestions into comments gitlab-ci: Check building ppc64 without TCG FreeBSD: Upgrade to 12.4 release tests/qtest: Enable qtest build on Windows .gitlab-ci.d/windows.yml: Exclude qTests from 64-bit CI job for now .gitlab-ci.d/windows.yml: Keep 64-bit and 32-bit build scripts consistent .gitlab-ci.d/windows.yml: Unify the prerequisite packages tests/qtest/libqos/e1000e: Correctly group register accesses tests/qtest/e1000e-test: De-duplicate constants tests/qtest/libqos/e1000e: Remove "other" interrupts hw: Include the VMWare devices only in the x86 targets MAINTAINERS: Add documentation files to the corresponding sections util/oslib-win32: Remove obsolete reference to g_poll code util/qemu-config: Fix "query-command-line-options" to provide the right values scripts/make-release: Only clone single branches to speed up the script scripts/make-release: Add a simple help text for the script monitor/misc: Remove superfluous include statements target/s390x: The MVCP and MVCS instructions are not privileged target/s390x/tcg/mem_helper: Test the right bits in psw_key_valid() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15Merge tag 'pull-target-arm-20221215-1' of ↵Peter Maydell3-2/+4
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue:  * hw/arm/virt: Add properties to allow more granular configuration of use of highmem space  * target/arm: Add Cortex-A55 CPU  * hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement  * Implement FEAT_EVT  * Some 3-phase-reset conversions for Arm GIC, SMMU  * hw/arm/boot: set initrd with #address-cells type in fdt  * hw/misc: Move some arm-related files from specific_ss into softmmu_ss  * Restrict arm_cpu_exec_interrupt() to TCG accelerator # gpg: Signature made Thu 15 Dec 2022 17:38:36 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20221215-1' of https://git.linaro.org/people/pmaydell/qemu-arm: (28 commits) target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator hw/misc: Move some arm-related files from specific_ss into softmmu_ss hw/arm/boot: set initrd with #address-cells type in fdt hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset target/arm: Report FEAT_EVT for TCG '-cpu max' target/arm: Implement HCR_EL2.TID4 traps target/arm: Implement HCR_EL2.TICAB,TOCU traps target/arm: Implement HCR_EL2.TTLBOS traps target/arm: Implement HCR_EL2.TTLBIS traps target/arm: Allow relevant HCR bits to be written for FEAT_EVT hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement target/arm: Add Cortex-A55 CPU ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15hw/misc: Move some arm-related files from specific_ss into softmmu_ssThomas Huth1-1/+1
The header target/arm/kvm-consts.h checks CONFIG_KVM which is marked as poisoned in common code, so the files that include this header have to be added to specific_ss and recompiled for each, qemu-system-arm and qemu-system-aarch64. However, since the kvm headers are only optionally used in kvm-constants.h for some sanity checks, we can additionally check the NEED_CPU_H macro first to avoid the poisoned CONFIG_KVM macro, so kvm-constants.h can also be used from "common" files (without the sanity checks - which should be OK since they are still done from other target-specific files instead). This way, and by adjusting some other include statements in the related files here and there, we can move some files from specific_ss into softmmu_ss, so that they only need to be compiled once during the build process. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221202154023.293614-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15block: GRAPH_RDLOCK for functions only called by co_wrappersKevin Wolf1-11/+9
The generated coroutine wrappers already take care to take the lock in the non-coroutine path, and assume that the lock is already taken in the coroutine path. The only thing we need to do for the wrapped function is adding the GRAPH_RDLOCK annotation. Doing so also allows us to mark the corresponding callbacks in BlockDriver as GRAPH_RDLOCK_PTR. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221207131838.239125-19-kwolf@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-12-15block: use co_wrapper_mixed_bdrv_rdlock in functions taking the rdlockEmanuele Giuseppe Esposito1-22/+31
Take the rdlock already, before we add the assertions. All these functions either read the graph recursively, or call BlockDriver callbacks that will eventually need to be protected by the graph rdlock. Do it now to all functions together, because many of these recursively call each other. For example, bdrv_co_truncate calls BlockDriver->bdrv_co_truncate, and some driver callbacks implement their own .bdrv_co_truncate by calling bdrv_flush inside. So if bdrv_flush asserts but bdrv_truncate does not take the rdlock yet, the assertion will always fail. Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221207131838.239125-18-kwolf@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-12-15block-coroutine-wrapper.py: introduce annotations that take the graph rdlockEmanuele Giuseppe Esposito1-1/+8
Add co_wrapper_bdrv_rdlock and co_wrapper_mixed_bdrv_rdlock option to the block-coroutine-wrapper.py script. This "_bdrv_rdlock" option takes and releases the graph rdlock when a coroutine function is created. This means that when used together with "_mixed", the function marked with co_wrapper_mixed_bdrv_rdlock will support both coroutine and non-coroutine case, and in the latter case it will create a coroutine that takes and releases the rdlock. When called from a coroutine, the caller must already hold the graph lock. Example: void co_wrapper_mixed_bdrv_rdlock bdrv_f1(); Becomes static void bdrv_co_enter_f1() { bdrv_graph_co_rdlock(); bdrv_co_function(); bdrv_graph_co_rdunlock(); } void bdrv_f1() { if (qemu_in_coroutine) { assume_graph_lock(); bdrv_co_function(); } else { qemu_co_enter(bdrv_co_enter_f1); ... } } When used alone, the function will not work in coroutine context, and when called in non-coroutine context it will create a new coroutine that takes care of taking and releasing the rdlock automatically. Example: void co_wrapper_bdrv_rdlock bdrv_f1(); Becomes static void bdrv_co_enter_f1() { bdrv_graph_co_rdlock(); bdrv_co_function(); bdrv_graph_co_rdunlock(); } void bdrv_f1() { assert(!qemu_in_coroutine()); qemu_co_enter(bdrv_co_enter_f1); ... } About their usage: - co_wrapper does not take the rdlock, so it can be used also outside the block layer. - co_wrapper_mixed will be used by many blk_* functions, since the coroutine function needs to call blk_wait_while_drained() and the rdlock *must* be taken afterwards, otherwise it's a deadlock. In the future this annotation will go away, and blk_* will use co_wrapper directly. - co_wrapper_bdrv_rdlock will be used by BlockDriver callbacks, ideally by all of them in the future. - co_wrapper_mixed_bdrv_rdlock will be used by the remaining functions that are still called by coroutine and non-coroutine context. In the future this annotation will go away, as we will split such mixed functions. Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221207131838.239125-17-kwolf@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-12-15Mark assert_bdrv_graph_readable/writable() GRAPH_RD/WRLOCKKevin Wolf2-4/+4
Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221207131838.239125-16-kwolf@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-12-15graph-lock: TSA annotations for lock/unlock functionsKevin Wolf1-10/+70
Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221207131838.239125-15-kwolf@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-12-15block: assert that graph read and writes are performed correctlyEmanuele Giuseppe Esposito2-17/+15
Remove the old assert_bdrv_graph_writable, and replace it with the new version using graph-lock API. See the function documentation for more information. Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221207131838.239125-14-kwolf@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-12-15clang-tsa: Add macros for shared locksKevin Wolf1-0/+4
Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221207131838.239125-8-kwolf@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-12-15clang-tsa: Add TSA_ASSERT() macroKevin Wolf1-0/+9
Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221207131838.239125-7-kwolf@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-12-15Import clang-tsa.hKevin Wolf1-0/+101
This defines macros that allow clang to perform Thread Safety Analysis based on function and variable annotations that specify the locking rules. On non-clang compilers, the annotations are ignored. Imported tsa.h from the original repository with the pthread_mutex_t wrapper removed: https://github.com/jhi/clang-thread-safety-analysis-for-c.git Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221207131838.239125-6-kwolf@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-12-15graph-lock: Implement guard macrosEmanuele Giuseppe Esposito1-0/+66
Similar to the implementation in lockable.h, implement macros to automatically take and release the rdlock. Create the empty GraphLockable and GraphLockableMainloop structs only to use it as a type for G_DEFINE_AUTOPTR_CLEANUP_FUNC. Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221207131838.239125-4-kwolf@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-12-15graph-lock: Introduce a lock to protect block graph operationsPaolo Bonzini3-0/+149
Block layer graph operations are always run under BQL in the main loop. This is proved by the assertion qemu_in_main_thread() and its wrapper macro GLOBAL_STATE_CODE. However, there are also concurrent coroutines running in other iothreads that always try to traverse the graph. Currently this is protected (among various other things) by the AioContext lock, but once this is removed, we need to make sure that reads do not happen while modifying the graph. We distinguish between writer (main loop, under BQL) that modifies the graph, and readers (all other coroutines running in various AioContext), that go through the graph edges, reading ->parents and->children. The writer (main loop) has "exclusive" access, so it first waits for any current read to finish, and then prevents incoming ones from entering while it has the exclusive access. The readers (coroutines in multiple AioContext) are free to access the graph as long the writer is not modifying the graph. In case it is, they go in a CoQueue and sleep until the writer is done. If a coroutine changes AioContext, the counter in the original and new AioContext are left intact, since the writer does not care where the reader is, but only if there is one. As a result, some AioContexts might have a negative reader count, to balance the positive count of the AioContext that took the lock. This also means that when an AioContext is deleted it may have a nonzero reader count. In that case we transfer the count to a global shared counter so that the writer is always aware of all readers. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221207131838.239125-3-kwolf@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-12-15block: Factor out bdrv_drain_all_begin_nopoll()Kevin Wolf1-0/+1
Provide a separate function that just quiesces the users of a node to prevent new requests from coming in, but without waiting for the already in-flight I/O to complete. This function can be used in contexts where polling is not allowed. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221207131838.239125-2-kwolf@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-12-15block/dirty-bitmap: convert coroutine-only functions to co_wrapperEmanuele Giuseppe Esposito3-6/+19
bdrv_can_store_new_dirty_bitmap and bdrv_remove_persistent_dirty_bitmap check if they are running in a coroutine, directly calling the coroutine callback if it's the case. Except that no coroutine calls such functions, therefore that check can be removed, and function creation can be offloaded to c_w. Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Message-Id: <20221128142337.657646-15-eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>