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2025-02-10Merge tag 'pull-target-arm-20250210' of ↵Stefan Hajnoczi1-1/+3
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Deprecate pxa2xx CPUs, iwMMXt emulation, -old-param option * Drop unused AArch64DecodeTable typedefs * Minor code cleanups * hw/net/cadence_gem: Fix the mask/compare/disable-mask logic * linux-user: Do not define struct sched_attr if libc headers do # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmeqH/sZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3lW6D/4r4SyxAzrjIQRLh3xydADN # A9EsQ44Or/M7jJ7uzR5nkLldlHdKTccVZFj17BlK6DnklsTUVSUoxpHtzYTHE2Ar # Q8iqV4dqoyDrYpqHWNQQvwQCBLbcj0CFQ1VjieG656m4uhImoeVMiH3xbFvMwqj0 # KpIWL/+jaRs5jgpnN7Ig4Zq3gVHVZWyOOjzIKF/l4hFchK4eao0oAWdWo/TtGPHB # WyqkO1YZoZGBlT/7WXyKE5YXoXbd8m079NXcHmH6sy1/fSNXQ7qIlHGV/36kiJo1 # WnDgZ0KUOEl4thaeq731xtgGcwt9C9Qx8g9bJP42os7EzQZBtvXxJXWgQKpvpNVH # Hmpsj0ed7oI1LH5DEPkqvYOEnnvEFt3skMbblhIZufnrAnojk9Q64v/Z1LNEIuuC # j5sZrFZsKPsA2uNzsmqXyJxWwnU6IT5YNBZAzALFTwE8dNL/VMXfRYhhUEy0Ay3C # jVXHk+sfOKo83YNswffagBeb/tRFDApgvRySxxL9TCONGl0HNkXqSuE+hssF8jyr # AnZ3zxSrmWKZizuotvFwaP0bxP0Sa/yeR1lR6E1xu+iEEJKJ4dE5xpX4E3uf6tHk # cfQQXFrhOzEwGn4qLDuqcgvhxRecZL7kNiFYidynKafIBw///J1cpaDYxxwh9v6O # TZuJliw0uCo6z0sXxVIn1w== # =MS2g # -----END PGP SIGNATURE----- # gpg: Signature made Mon 10 Feb 2025 10:49:15 EST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250210' of https://git.linaro.org/people/pmaydell/qemu-arm: linux-user: Do not define struct sched_attr if libc headers do qemu-options: Deprecate -old-param command line option hw/net/cadence_gem: Fix the mask/compare/disable-mask logic hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE hw/arm/fsl-imx7: Add local 'mpcore/gic' variables hw/arm/fsl-imx6ul: Add local 'mpcore/gic' variables hw/arm/fsl-imx6: Add local 'mpcore/gic' variables hw/arm/boot: Propagate vCPU to arm_load_dtb() target/arm: Drop unused AArch64DecodeTable typedefs tests/tcg/arm: Remove test-arm-iwmmxt test target/arm: deprecate the pxa2xx CPUs and iwMMXt emulation Conflicts: - The iwMMXt deprecation notice conflicted with the 32-bit host operating system deprecation notice. Add both notices. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-02-07hw/arm/boot: Propagate vCPU to arm_load_dtb()Philippe Mathieu-Daudé1-1/+3
In heterogeneous setup the first vCPU might not be the one expected, better pass it explicitly. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 20250130112615.3219-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-04hw/pci-host/astro: Add LMMIO range supportHelge Deller1-3/+3
Each Astro on 64-bit machines supports up to four LMMIO regions. Those regions are used by graphic cards and other PCI devices which need to map huge memory areas. The LMMIO regions are configured and set up by SeaBIOS-hppa and then used as-is by the operating systems (Linux, HP-UX). With this addition it's now possible to add other PCI graphic cards on the command line, e.g. with "-device ati-vga". Signed-off-by: Helge Deller <deller@gmx.de>
2025-02-02Merge tag 'hw-misc-20250131' of https://github.com/philmd/qemu into stagingStefan Hajnoczi6-80/+28
Misc HW patches - Remove uses of &first_cpu in rx-gdbsim and loongson3_virt machines (Philippe) - Convert few legacy qemu_allocate_irqs to qemu_init_irqs (Philippe) - Add tracing events in i2c-echo device (Titus) - Fix debug format string in USB EHCI (Zoltan) - Rework loader API to remove its target_words_bigendian() call (Philippe) - QOMify OMAP MMC device (Peter) - Remove legacy SD Card APIs (Peter) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmedOmkACgkQ4+MsLN6t # wN4qHhAAtL3vmk6hQgKD76bSaB3CDEdHsnS7qqeRVVmbr7pQL9D6yyXzkjJBzZtk # nG7ubhoS5WFeKswzD8tY/mgP25hntnq38TNrRxDrpRNdFYF+a2cncpRGfgzk0z/9 # nme/BuUx6fNowV8MVGLNOLvaDCeDHl9biTLJmcQyqwlHy9l9Wi6DSa6Xi9ZQWlHi # fxYVeuQ7HYlKwhiu3mqpfNeauIgMSWz8V48ETCrFnjMWmiF1k1L0GccWDS8zpPDk # QkdOxHC4eVMxk0d2458eUXeqo/izfzoc7Z9hW6W8cyI69y4m011xqANd/udTS03E # HMcG9Ks0E+Yw8NGoErOP7zu8yFVEzCn2BKhH/wrUHBC2UfP99vNR/b8LNkg25y19 # IItOkMban0Oyr9KaNb1Ga+3pZIsyyil+shSYNHpWkfqk+TUpZkMUSaVHA9r1oB3V # u/dOO/lPLaWMvftKVXRl3K/Lfz4WF5cWjza5RratnzbBqqwr03CwjjBEuZIX/5ww # ATj/fV10OSHScxCqauYp8uuNSgEOKaJCJe2uEMaLvxn/O9ka0FQZ5CLUJ0yIKs/t # Tg4sS0QLgmpaXwSnscKoVE7aHWNFT1WomHI4SjWbwUQhmm0DmPizBZ2yX8dnSR24 # ubtzmxNYFWScrUTGQvbMhkU6I+Sc0Ca8APmPxErNV2mzF4p3CPE= # =Jvwi # -----END PGP SIGNATURE----- # gpg: Signature made Fri 31 Jan 2025 16:02:33 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20250131' of https://github.com/philmd/qemu: (36 commits) hw/sd: Remove unused SDState::enable hw/sd: Remove unused legacy functions, stop killing mammoths hw/sd: Remove unused 'enable' method from SDCardClass hw/sd/omap_mmc: Untabify hw/sd/omap_mmc: Remove unused coverswitch qemu_irq hw/arm/omap1: Inline creation of MMC hw/sd/omap_mmc: Use similar API for "wire up omap_clk" to other OMAP devices hw/sd/omap_mmc: Convert to SDBus API hw/sd/omap_mmc: Convert output qemu_irqs to gpio and sysbus IRQ APIs hw/sd/omap_mmc: Convert remaining 'struct omap_mmc_s' uses to OMAPMMCState hw/sd/omap_mmc: Do a minimal conversion to QDev hw/loader: Pass ELFDATA endian order argument to load_elf() hw/loader: Pass ELFDATA endian order argument to load_elf_as() hw/loader: Pass ELFDATA endian order argument to load_elf_ram_sym() hw/loader: Clarify local variable name in load_elf_ram_sym() hw/loader: Remove unused load_elf_ram() hw/avr/boot: Replace load_elf_ram_sym() -> load_elf_as() hw/usb/hcd-ehci: Fix debug printf format string hw/misc/i2c-echo: add tracing hw/char/pci-multi: Convert legacy qemu_allocate_irqs to qemu_init_irq ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-31hw/sd: Remove unused legacy functions, stop killing mammothsPeter Maydell1-50/+0
The sdcard_legacy.h header defines function prototypes for the "legacy" SD card API, which was used by non-qdevified SD controller models. We've now converted the only remaining non-qdev SD controller, so we can drop the legacy API. Entirely unused functions: sd_init(), sd_set_cb(), sd_enable() Functions which now become static inside sd.c (they are the underlying implementations of methods on SDCardClass): sd_do_command(), sd_write_byte(), sd_read_byte() Removal of sd_init() means that we can also remove the me_no_qdev_me_kill_mammoth_with_rocks flag, the codepaths that were only reachable when it was set, and the inserted_cb and readonly_cb qemu_irq lines that went with that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250128104519.3981448-11-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-01-31hw/sd: Remove unused 'enable' method from SDCardClassPeter Maydell1-1/+0
The SDCardClass has an 'enable' method, but nothing actually invokes it. The underlying implementation is sd_enable(), which is documented in sdcard_legacy.h as something that should not be used and was only present for the benefit of the now-removed nseries boards. Unlike all the other method pointers in SDCardClass, this one doesn't have an sdbus_foo() function wrapper in hw/sd/core.c. Remove the unused method. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250128104519.3981448-10-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-01-31hw/sd/omap_mmc: Use similar API for "wire up omap_clk" to other OMAP devicesPeter Maydell1-0/+3
The approach we've settled on for handling the omap_clk wiring for OMAP devices converted to QDev is to have a function omap_foo_set_clk() whose implementation just sets the field directly in the device's state struct. (See the "TODO" comment near the top of omap.h.) Make omap_mmc do the same. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250128104519.3981448-6-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-01-31hw/sd/omap_mmc: Convert to SDBus APIPeter Maydell1-1/+0
Convert the OMAP MMC controller to the new SDBus API: * the controller creates an SDBus bus * instead of sd_foo functions on the SDState object, call sdbus_foo functions on the SDBus * the board code creates a proper TYPE_SD_CARD object and attaches it to the controller's SDBus, instead of the controller creating a card directly via sd_init() that never gets attached to any bus * because the SD card object is on a bus, it gets reset automatically by the "traverse the qbus tree resetting things" code, and we don't need to manually reset the card from the controller reset function Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250128104519.3981448-5-peter.maydell@linaro.org> [PMD: Include "hw/sd/sd.h" instead of "hw/sd/sdcard_legacy.h", create bus in omap_mmc_initfn() instead of omap_mmc_realize()] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-01-31hw/sd/omap_mmc: Convert remaining 'struct omap_mmc_s' uses to OMAPMMCStatePeter Maydell1-1/+1
Mechanically convert the remaining uses of 'struct omap_mmc_s' to 'OMAPMMCState'. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250128104519.3981448-3-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-01-31hw/sd/omap_mmc: Do a minimal conversion to QDevPeter Maydell1-7/+8
Do a minimal conversion of the omap_mmc device model to QDev. In this commit we do the bare minimum to produce a working device: * add the SysBusDevice parent_obj and the usual type boilerplate * omap_mmc_init() now returns a DeviceState* * reset is handled by sysbus reset, so the SoC reset function doesn't need to call omap_mmc_reset() any more * code that should obviously be in init/realize is moved there from omap_mmc_init() We leave various pieces of cleanup to later commits: * rationalizing 'struct omap_mmc_s *' to 'OMAPMMCState *' * using gpio lines rather than having omap_mmc_init() directly set s->irq, s->dma * switching away from the legacy SD API and instead having the SD card plugged into a bus Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250128104519.3981448-2-peter.maydell@linaro.org> [PMD: Do not add omap_mmc_realize()] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-01-31hw/loader: Pass ELFDATA endian order argument to load_elf()Philippe Mathieu-Daudé1-1/+1
Rather than passing a boolean 'is_big_endian' argument, directly pass the ELFDATA, which can be unspecified using the ELFDATANONE value. Update the call sites: 0 -> ELFDATA2LSB 1 -> ELFDATA2MSB TARGET_BIG_ENDIAN -> TARGET_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250127113824.50177-7-philmd@linaro.org>
2025-01-31hw/loader: Pass ELFDATA endian order argument to load_elf_as()Philippe Mathieu-Daudé1-1/+1
Rather than passing a boolean 'is_big_endian' argument, directly pass the ELFDATA, which can be unspecified using the ELFDATANONE value. Update the call sites: 0 -> ELFDATA2LSB 1 -> ELFDATA2MSB Note, this allow removing the target_words_bigendian() call in the GENERIC_LOADER device, where we pass ELFDATANONE. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250127113824.50177-6-philmd@linaro.org>
2025-01-31hw/loader: Pass ELFDATA endian order argument to load_elf_ram_sym()Philippe Mathieu-Daudé1-2/+2
Rather than passing a boolean 'is_big_endian' argument, directly pass the ELFDATA, which can be unspecified using the ELFDATANONE value. Update the call sites: 0 -> ELFDATA2LSB Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250127113824.50177-5-philmd@linaro.org>
2025-01-31hw/loader: Remove unused load_elf_ram()Philippe Mathieu-Daudé1-13/+1
Last use of load_elf_ram() was removed in commit 188e255bf8e ("hw/s390x: Remove the possibility to load the s390-netboot.img binary"), remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20250127113824.50177-3-philmd@linaro.org>
2025-01-31hw/ipack: Remove legacy qemu_allocate_irqs() usePhilippe Mathieu-Daudé1-5/+2
No need to dynamically allocate IRQ when we know before hands how many we'll use. Declare the 2 of them in IPackDevice state and initialize them in the DeviceRealize handler. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250121155526.29982-4-philmd@linaro.org>
2025-01-31hw/irq: Introduce qemu_init_irqs() helperPhilippe Mathieu-Daudé1-0/+11
While qemu_init_irq() initialize a single IRQ, qemu_init_irqs() initialize an array of them. Suggested-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250121155526.29982-2-philmd@linaro.org>
2025-01-30Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into stagingStefan Hajnoczi2-5/+3
trivial patches for 2025-01-30 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEZKoqtTHVaQM2a/75gqpKJDselHgFAmebf70ACgkQgqpKJDse # lHgmWw/8DZXr5+Aar9FJZIUZWqxBxRzNjnvKEGQPCKI+Iqi3qkwOHij3Tr06vERM # upWZ/6Gx6v8SFjlfCv4VvtAHwflLOFqBzDxrCRDiZqNuLDaXuLnTMF1H8teg4ciM # 7uPjvI17LDgoBEDR27divxcLcP4dDI5RMkAndzyL1U9OGugO4vgmDUAuXkNzqBFS # tnWQmay3VTDVNtd4YJvhqJM5UR/4mSHlISlZpbzpF2Pxd2Job6IHYEzmre+0iteQ # TukjKkSQ7os7jEV984zVmwZnqCZrq6iIjX0nY6d1wWeDLjRMzLNqHuZ7jYVYDMWr # G/HdXp7BfGW1kG67W86MWWVW6O96DsyN5e76pMdlu8DjDs1/hiTA02cUEa2x2Alw # 3ngblJMC2JhvmuMLZStJf3zTb1GABijQJdfEYjUJ1FEY0dhVuK5teeTRjql7xjnw # tHtaxn11ahifZ++kRAeZyinkkUlKLOcV8xoGqmv8uRjy6XepFASFkSj/jEbyohKF # BGGvUVT1cp0Krr9TOAEnrhYEpXgHjxsR0PqTphH1wQojr/AyYTBwSy/wGWPbMvQQ # u/hHoJ/RgiiSf5HW/PRUbWrTdgYPg8Ej/9n7geAZSk2e9hfGI6Ii88XOmrZefQ+4 # 2GQ+a3I2n4LQ1cyzrGZgUncwLClIpqN/WtRsUNEFQs6zrcvG52U= # =2d/y # -----END PGP SIGNATURE----- # gpg: Signature made Thu 30 Jan 2025 08:33:49 EST # gpg: using RSA key 64AA2AB531D56903366BFEF982AA4A243B1E9478 # gpg: Good signature from "Michael Tokarev <mjt@debian.org>" [unknown] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [unknown] # gpg: aka "Michael Tokarev <mjt@tls.msk.ru>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 9D8B E14E 3F2A 9DD7 9199 28F1 61AD 3D98 ECDF 2C8E # Subkey fingerprint: 64AA 2AB5 31D5 6903 366B FEF9 82AA 4A24 3B1E 9478 * tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: hw/i386/pc: Remove unused pc_compat_2_3 declarations licenses: Remove SPDX tags not being license identifier for Linaro tests/functional/test_mips_malta: Fix comment about endianness of the test gdbstub/user-target: fix gdbserver int format (%d -> %x) vvfat: create_long_filename: fix out-of-bounds array access net/dump: Correctly compute Ethernet packet offset net: Fix announce_self Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-30Merge tag 'migration-20250129-pull-request' of ↵Stefan Hajnoczi1-0/+1
https://gitlab.com/farosas/qemu into staging Migration pull request - Purge of ram_save_target_page_legacy - Cleanups to postcopy, json writer, migration states - New migration mode cpr-transfer - Fix for a -Werror=maybe-uninitialized instance in savevm # -----BEGIN PGP SIGNATURE----- # # iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmeaT8EQHGZhcm9zYXNA # c3VzZS5kZQAKCRDHmNx0G+wxndXrEACTT+rdoEvOsNs4nM2a67GjxUoQZVTAWn+8 # lYhhNZLA4E+qHwpHTDCwyfyvCe615r72+bF7QO1KTrYeXGJg4SPk5kbEhCDqqjEu # SGqrlPwkC1x3WkTvb228iDddDQ8dccko3Sy6wAyz0o8dtp5p4iK+57qzB/84u94L # y3zQ+owOo9OLnXgdfMpN99HGQSvPR7CbP/2L293IrMCuPDUo9XhI7ARNS/phbT3Z # aDl10WGHKz1SJWOkPj137E6+xMKuCmOZDTufTcTaHfyliD04JRWgEZVnKJxKJDxd # 9e+lzHvXuYfO7YO11fr7DttPRnLEfjipELVTxrudM92eZ95XwdL4+ggfBTGHt76P # yFUrp7G8qsUjWd+DHPmoo6Gx71zPbE6v9J2NMn2/1k4WdPOYy7HTmDgCkRirRTvV # irYkHtdSFFsj3c0g4P4mhOzXnvUkGXzgrjteM5hlLy3bjSeZz9VMZADjiGqFGVPb # 6euPcLLa9oynkoP5UXmFd/9PjWcgnfIbQu2MVlIyWhjvTGZKSGecVZmH5pWTJuBV # xCbab1jYprRFpUIAMo94rgvRQRosomS1+GjGndFkX5++dTTlFSqpDLSGcEnPSGRx # o9n+IldNiqh2vjN1bj60pLfmrHN/F+hsGTsDJlW+kfeyBXBkGArg1rDjN5ae7GvD # UZK0N+OG0g== # =jwOI # -----END PGP SIGNATURE----- # gpg: Signature made Wed 29 Jan 2025 10:56:49 EST # gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D # gpg: issuer "farosas@suse.de" # gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown] # gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D * tag 'migration-20250129-pull-request' of https://gitlab.com/farosas/qemu: (42 commits) migration: refactor ram_save_target_page functions migration: Trivial cleanup on JSON writer of vmstate_save() migration: Merge precopy/postcopy on switchover start migration: Always set DEVICE state migration: Cleanup qemu_savevm_state_complete_precopy() migration: Unwrap qemu_savevm_state_complete_precopy() in postcopy migration: Notify COMPLETE once for postcopy migration: Take BQL slightly longer in postcopy_start() migration: Drop cached migration state in migration_maybe_pause() migration: Adjust locking in migration_maybe_pause() migration: Adjust postcopy bandwidth during switchover migration: Synchronize all CPU states only for non-iterable dump migration: Drop inactivate_disk param in qemu_savevm_state_complete* migration: Avoid two src-downtime-end tracepoints for postcopy migration: Optimize postcopy on downtime by avoiding JSON writer migration: Do not construct JSON description if suppressed migration: Remove postcopy implications in should_send_vmdesc() migration: cpr-transfer documentation migration-test: cpr-transfer tests/qtest: assert qmp connected ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-30hw/i386/pc: Remove unused pc_compat_2_3 declarationsPhilippe Mathieu-Daudé1-3/+0
We removed the implementations in commit 46a2bd52571 ("hw/i386/pc: Remove deprecated pc-i440fx-2.3 machine") but forgot to remove the declarations. Do it now. Fixes: 46a2bd52571 ("hw/i386/pc: Remove deprecated pc-i440fx-2.3 machine") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2025-01-30licenses: Remove SPDX tags not being license identifier for LinaroPhilippe Mathieu-Daudé1-2/+3
Per [*]: "we're only interested in adopting SPDX for recording the licensing info, [not] any other SPDX metadata." Replace the 'SPDX-FileCopyrightText' and 'SPDX-FileContributor' tags added by Linaro by 'Copyright (c)' and 'Authors' words respectively. [*] https://lore.kernel.org/qemu-devel/20241007154548.1144961-4-berrange@redhat.com/ Inspired-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2025-01-29Merge tag 'pull-target-arm-20250128-1' of ↵Stefan Hajnoczi5-4/+9
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/arm: Remove various uses of first_cpu global * hw/char/imx_serial: Fix reset value of UFCR register * hw/char/imx_serial: Update all state before restarting ageing timer * hw/pci-host/designware: Expose MSI IRQ * hw/arm/stellaris: refactoring, cleanup * hw/arm/stellaris: map both I2C controllers * tests/functional: Add a test for the arm microbit machine * target/arm: arm_reset_sve_state() should set FPSR, not FPCR * target/arm: refactorings preparatory to FEAT_AFP implementation * fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed * fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed * hw/usb/canokey: Fix buffer overflow for OUT packet # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmeZOi0ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3sUeEACwDhM4ldn/gVZgVN7nf42a # /CLD/qJx1vqi5bAB5zkY1bSCR9hS2IkhTBoQQH9Ng6ztG1IRpT/tKXDJAemWty70 # XgExdl4yjdwXMQK4JKU9qSfaBTuX7Z8Hz+nA1AnblO/4H+XpVNVJzp8Ee/uWTyEd # BKPBpwqbIXNwUWEqkzDok074Q05rHlhsJD2DsoJTcmtpROhLHLATwQDZGGFuf56H # LVcdx6GRP+/mWEGWLtj19mvaR/2cn4rQf+I1MACZ81nRjQCHbCohNAMr2wFsKg1+ # 2jYk9uHdFoambJ5+mFuC55Efk+QJaP4vDR0Gf3jLloFr+rS/5h3HiUuD8dUWOwFd # mPWXsjwYzqBW2knt1nfq1ByzYWZ8rVQEn5G53dX/eoNXuDGsonZxPnevgmv5kIUc # /W618Jez1nu9RDtNKccobHEtTGlGInJxJ7YzkU7Q6FO80IAqSdV7t9v7uPLJwcnz # nQz+wVzb4oOmwMzn3BpKY7N/S7IZOSy3ASNHj8o4yCHMJT8Ki0/N4bl0k0DLxJ0T # RiNCsV9c7MJfo9a+pbOnu0Lc3SjjropdvHYU+bB7R0mgd8ysN+Tou0dpa+i7tUTu # DHWqs2/+UApHKBiC+DSynPjjRR2aT/5lYFncGaiEVoEQttPLka3SAzgHPVQZs1zD # bxZkEAFktAFGIjU70fYNkg== # =H4p7 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 28 Jan 2025 15:12:29 EST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250128-1' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/usb/canokey: Fix buffer overflow for OUT packet target/arm: Use FPST_A64_F16 for halfprec-to-other conversions target/arm: Remove redundant advsimd float16 helpers fpu: Fix a comment in softfloat-types.h fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed target/arm: Remove now-unused vfp.fp_status_f16 and FPST_FPCR_F16 target/arm: Use FPST_A64_F16 in A64 decoder target/arm: Use FPST_A32_F16 in A32 decoder target/arm: Use fp_status_f16_a64 in AArch64-only helpers target/arm: Use fp_status_f16_a32 in AArch32-only helpers target/arm: Define new fp_status_f16_a32 and fp_status_f16_a64 target/arm: Remove now-unused vfp.fp_status and FPST_FPCR target/arm: Use FPST_A64 in A64 decoder target/arm: Use FPST_A32 in A32 decoder target/arm: Use fp_status_a32 in vfp_cmp helpers target/arm: Use fp_status_a32 in vjvct helper target/arm: Use fp_status_a64 or fp_status_a32 in is_ebf() target/arm: Use vfp.fp_status_a64 in A64-only helper functions target/arm: Define new fp_status_a32 and fp_status_a64 ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-29machine: aux-ram-share optionSteve Sistare1-0/+1
Allocate auxilliary guest RAM as an anonymous file that is shareable with an external process. This option applies to memory allocated as a side effect of creating various devices. It does not apply to memory-backend-objects, whether explicitly specified on the command line, or implicitly created by the -m command line option. This option is intended to support new migration modes, in which the memory region can be transferred in place to a new QEMU process, by sending the memfd file descriptor to the process. Memory contents are preserved, and if the mode also transfers device descriptors, then pages that are locked in memory for DMA remain locked. This behavior is a pre-requisite for supporting vfio, vdpa, and iommufd devices with the new modes. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/1736967650-129648-7-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-01-27hw/pci-host/designware: Expose MSI IRQBernhard Beschow3-2/+7
Fixes INTD and MSI interrupts poking the same IRQ line without keeping track of each other's IRQ level. Furthermore, SoCs such as the i.MX 8M Plus don't share the MSI IRQ with the INTx lines, so expose it as a dedicated pin. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/char/imx_serial: Fix reset value of UFCR registerBernhard Beschow1-1/+1
The value of the UCFR register is respected when echoing characters to the terminal, but its reset value is reserved. Fix the reset value to the one documented in the datasheet. While at it move the related attribute out of the section of unimplemented registers since its value is actually respected. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m'Philippe Mathieu-Daudé1-1/+1
The ARMv7MState object is not simply a CPU, it also contains the NVIC, SysTick timer, and various MemoryRegions. Rename the field as 'armv7m', like other Cortex-M boards. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20250112225614.33723-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/timer/aspeed: Add AST2700 SupportJamin Lin1-0/+1
The timer controller include 8 sets of 32-bit decrement counters, based on either PCLK or 1MHZ clock and the design of timer controller between AST2600 and AST2700 are almost the same. TIMER0 – TIMER7 has their own individual control and interrupt status register. In other words, users are able to set timer control in register TMC10 with different TIMER base address and clear timer control and interrupt status in register TMC14 with different TIMER base address. Introduce new "aspeed_2700_timer_read" and "aspeed_2700_timer_write" callback functions and a new ast2700 class to support AST2700. The base address of TIMER0 to TIMER7 as following. Base Address of Timer 0 = 0x12C1_0000 Base Address of Timer 1 = 0x12C1_0040 Base Address of Timer 2 = 0x12C1_0080 Base Address of Timer 3 = 0x12C1_00C0 Base Address of Timer 4 = 0x12C1_0100 Base Address of Timer 5 = 0x12C1_0140 Base Address of Timer 6 = 0x12C1_0180 Base Address of Timer 7 = 0x12C1_01C0 The register address space of each TIMER is "0x40" , and uses the following formula to get the index and register of each TIMER. timer_index = offset >> 6; timer_offset = offset & 0x3f; The TMC010 is a counter control set and interrupt status register. Write "1" to TMC10[3:0] will set the specific bits to "1". Introduce a new "aspeed_2700_timer_set_ctrl" function to handle this register behavior. The TMC014 is a counter control clear and interrupt status register, to clear the specific bits to "0", it should write "1" to TMC14[3:0] on the same bit position. Introduce a new "aspeed_2700_timer_clear_ctrl" function to handle this register behavior. TMC014 does not support read operation. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Acked-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20250113064455.1660564-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-27hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVBJamin Lin1-0/+1
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2600 EVB, the Write Protected pin is active high by default. To support it, introduces a new "sdhci_wp_inverted" property in ASPEED MACHINE State and set it true for AST2600 EVB and set "wp_inverted" property true of sdhci-generic model. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20241114094839.4128404-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-27hw/sd/sdhci: Introduce a new Write Protected pin inverted propertyJamin Lin1-0/+5
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). However, some boards are design Write Protected pin active high. In other words, write enable the bit 19 should be 0 and write protected the bit 19 should be 1 at the Present State Register (0x24). To support it, introduces a new "wp-inverted" property and set it false by default. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Acked-by: Cédric Le Goater <clg@redhat.com> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20241114094839.4128404-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-19target/riscv: Handle Smrnmi interrupt and exceptionTommy Wu1-0/+4
Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their expectation. This patch also adds the functionality to handle the RNMI signals. Signed-off-by: Frank Chang <frank.chang@sifive.com> Signed-off-by: Tommy Wu <tommy.wu@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250106054336.1878291-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-01-17Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi2-4/+28
* rust: miscellaneous changes * target/i386: small code generation improvements * target/i386: various cleanups and fixes * cpu: remove env->nr_cores # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmeBoIgUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOD2gf+NK7U1EhNIrsbBsbtu2i7+tnbRKIB # MTu+Mxb2wz4C7//pxq+vva4bgT3iOuL9RF19PRe/63CMD65xMiwyyNrEWX2HbRIJ # 5dytLLLdef3yMhHh2x1uZfm54g12Ppvn9kulMCbPawrlqWgg1sZbkUBrRtFzS45c # NeYjGWWSpBDe7LtsrgSRYLPnz6wWEiy3tDpu2VoDtjrE86UVDXwyzpbtBk9Y8jPi # CKdvLyQeO9xDE5OoXMjJMlJeQq3D9iwYEprXUqy+RUZtpW7YmqMCf2JQ4dAjVCad # 07v/kITF4brGCVnzDcDA6W7LqHpBu1w+Hn23yLw3HEDDBt11o9JjQCl9qA== # =xIQ4 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 10 Jan 2025 17:34:48 EST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (38 commits) i386/cpu: Set and track CPUID_EXT3_CMP_LEG in env->features[FEAT_8000_0001_ECX] i386/cpu: Set up CPUID_HT in x86_cpu_expand_features() instead of cpu_x86_cpuid() cpu: Remove nr_cores from struct CPUState i386/cpu: Hoist check of CPUID_EXT3_TOPOEXT against threads_per_core i386/cpu: Track a X86CPUTopoInfo directly in CPUX86State i386/topology: Introduce helpers for various topology info of different level i386/topology: Update the comment of x86_apicid_from_topo_ids() i386/cpu: Drop cores_per_pkg in cpu_x86_cpuid() i386/cpu: Drop the variable smp_cores and smp_threads in x86_cpu_pre_plug() i386/cpu: Extract a common fucntion to setup value of MSR_CORE_THREAD_COUNT target/i386/kvm: Replace ARRAY_SIZE(msr_handlers) with KVM_MSR_FILTER_MAX_RANGES target/i386/kvm: Clean up error handling in kvm_arch_init() target/i386/kvm: Return -1 when kvm_msr_energy_thread_init() fails target/i386/kvm: Clean up return values of MSR filter related functions target/i386/confidential-guest: Fix comment of x86_confidential_guest_kvm_type() target/i386/kvm: Drop workaround for KVM_X86_DISABLE_EXITS_HTL typo target/i386/kvm: Only save/load kvmclock MSRs when kvmclock enabled target/i386/kvm: Remove local MSR_KVM_WALL_CLOCK and MSR_KVM_SYSTEM_TIME definitions target/i386/kvm: Add feature bit definitions for KVM CPUID i386/cpu: Mark avx10_version filtered when prefix is NULL ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-16Merge tag 'pull-xenfv-20250116' of git://git.infradead.org/users/dwmw2/qemu ↵Stefan Hajnoczi2-0/+10
into staging Xen regression fixes and cleanups # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEMUsIrNDeSBEzpfKGm+mA/QrAFUQFAmeIxhcSHGR3bXdAYW1h # em9uLmNvLnVrAAoJEJvpgP0KwBVEbKoP/iqQ+PhbwT9+xz6lxW+g1Dx+YGrT/ugp # d3xHn9AEkR0EHC42J6RB/llyWbKVD/IIhYwUk5GDm+4InGrtuQDhG6UqWxqvIRht # 0JuZvVm7x5akmKv73igxNqZHVg0ZEAS+EllBUaBYWj0pvpMbBK93Sdz9PXKxA7Nm # dPeFrOpL2TAmnDCH1UuBbXypHEjAghmv7WFphMtk6qLX+wYVaK3F2J/ed2TNyT0V # LliOdQH0Pxt445SSVJIZRe9bW3FH7qyvZV1gCnxSnqPUlN7vBhpjzgl4hWEzVYcp # 7X21ZAD9kPc81DJjYucbLjAbrqSmlDrJqL05qtRigfPcnqz2NoKrYxhj8B0F8mgt # 1IbymPyeab5gk5Hi1QgMmG5eobDDaglDSxpq6gRfJBiJW+1adif00z/HVvt5onS0 # uQ6i6w5NzQciBX77muAb2ZDEMysjk+3wSJMMpkfl90D0kjlMqeWWs4FH9ThasjC+ # EhQioUD0euedgnzOSfQjNNtAW4gzv9rcShkcV84bjxP/0Es+Pgx9f6wtCUTzdeqy # Cid8/72lHIgrkZGfpv8BBZkA1XP09vgtUGKyAWm4yHOcB57l8cNiL1nKtqoCLwkQ # 8JWFWzFeEY19KoiRGY5saH6ExeOx8fmc/lYwqImZqFqvuFX4Vf2RJdTIRIYr7g05 # 2QffxFmskg+A # =Wz0V # -----END PGP SIGNATURE----- # gpg: Signature made Thu 16 Jan 2025 03:40:55 EST # gpg: using RSA key 314B08ACD0DE481133A5F2869BE980FD0AC01544 # gpg: issuer "dwmw@amazon.co.uk" # gpg: Good signature from "David Woodhouse <dwmw@amazon.co.uk>" [unknown] # gpg: aka "David Woodhouse <dwmw@amazon.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 314B 08AC D0DE 4811 33A5 F286 9BE9 80FD 0AC0 1544 * tag 'pull-xenfv-20250116' of git://git.infradead.org/users/dwmw2/qemu: system/runstate: Fix regression, clarify BQL status of exit notifiers hw/xen: Fix errp handling in xen_console hw/xen: Use xs_node_read() from xenstore_read_str() instead of open-coding it hw/xen: Use xs_node_read() from xen_netdev_get_name() hw/xen: Use xs_node_read() from xen_console_get_name() hw/xen: Use xs_node_read() from xs_node_vscanf() xen: do not use '%ms' scanf specifier hw/xen: Add xs_node_read() helper function Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-16Merge tag 'pull-loongarch-20250116' of https://gitlab.com/bibo-mao/qemu into ↵Stefan Hajnoczi2-1/+5
staging loongarch queue # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCZ4hk/QAKCRAfewwSUazn # 0WagAQDgJaWBLQxZkyQR2FQm3WHg3Uf/qolab9nDGo3b2BpixgD/RdvZf+mZpAwf # 2ipAQ7g5GqGTKtTAdqO/aBAqTCZCqQU= # =7KKt # -----END PGP SIGNATURE----- # gpg: Signature made Wed 15 Jan 2025 20:46:37 EST # gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1 # gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C # Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1 * tag 'pull-loongarch-20250116' of https://gitlab.com/bibo-mao/qemu: hw/intc/loongarch_ipi: Use alternative implemation for cpu_by_arch_id hw/intc/loongson_ipi: Add more input parameter for cpu_by_arch_id hw/intc/loongarch_ipi: Remove property num-cpu hw/intc/loongarch_ipi: Get cpu number from possible_cpu_arch_ids hw/intc/loongson_ipi: Remove property num_cpu from loongson_ipi_common hw/intc/loongson_ipi: Remove num_cpu from loongson_ipi_common hw/intc/loongarch_ipi: Implement realize interface target/loongarch: Add page table walker support for debugger usage Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-15hw/acpi: Add vmclock deviceDavid Woodhouse1-0/+34
The vmclock device addresses the problem of live migration with precision clocks. The tolerances of a hardware counter (e.g. TSC) are typically around ±50PPM. A guest will use NTP/PTP/PPS to discipline that counter against an external source of 'real' time, and track the precise frequency of the counter as it changes with environmental conditions. When a guest is live migrated, anything it knows about the frequency of the underlying counter becomes invalid. It may move from a host where the counter running at -50PPM of its nominal frequency, to a host where it runs at +50PPM. There will also be a step change in the value of the counter, as the correctness of its absolute value at migration is limited by the accuracy of the source and destination host's time synchronization. The device exposes a shared memory region to guests, which can be mapped all the way to userspace. In the first phase, this merely advertises a 'disruption_marker', which indicates that the guest should throw away any NTP synchronization it thinks it has, and start again. Because the region can be exposed all the way to userspace, applications can still use time from a fast vDSO 'system call', and check the disruption marker to be sure that their timestamp is indeed truthful. The structure also allows for the precise time, as known by the host, to be exposed directly to guests so that they don't have to wait for NTP to resync from scratch. The values and fields are based on the nascent virtio-rtc specification, and the intent is that a version (hopefully precisely this version) of this structure will be included as an optional part of that spec. In the meantime, a simple ACPI device along the lines of VMGENID is perfectly sufficient and is compatible with what's being shipped in certain commercial hypervisors. Linux guest support was merged into the 6.13-rc1 kernel: https://git.kernel.org/torvalds/c/205032724226 Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org> Message-Id: <07fd5e2f529098ad4d7cab1423fe9f4a03a9cc14.camel@infradead.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15vhost: Add stubs for the migration state transfer interfaceLaurent Vivier1-0/+23
Migration state transfer interface is only used by vhost-user-fs, so the interface needs to be defined only when vhost is built. But I need to use this interface with virtio-net and vhost is not always enabled, and to avoid undefined reference error during build, define stub functions for vhost_supports_device_state(), vhost_save_backend_state() and vhost_load_backend_state(). Cc: Hanna Czenczek <hreitz@redhat.com> Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20250115135044.799698-2-lvivier@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15acpi/ghes: better name the offset of the hardware error firmwareMauro Carvalho Chehab1-1/+1
The hardware error firmware is where HEST error structures are stored. Those can be GHESv2, but they can also be other types. Better name the location of the hardware error. No functional changes. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <ddbb94294bafee998f12fede3ba0b05dae5ee45f.1736945236.git.mchehab+huawei@kernel.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15acpi/ghes: better name GHES memory error functionMauro Carvalho Chehab1-2/+2
The current function used to generate GHES data is specific for memory errors. Give a better name for it, as we now have a generic function as well. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Message-Id: <35b59121129d5e99cb5062cc3d775594bbb0905b.1736945236.git.mchehab+huawei@kernel.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15acpi/ghes: make the GHES record generation more genericMauro Carvalho Chehab1-0/+3
Split the code into separate functions to allow using the common CPER filling code by different error sources. The generic code was moved to ghes_record_cper_errors(), and ghes_gen_err_data_uncorrectable_recoverable() now contains only a logic to fill the Generic Error Data part of the record, as described at: ACPI 6.2: 18.3.2.7.1 Generic Error Data The remaining code to generate a memory error now belongs to acpi_ghes_record_errors() function. A further patch will give it a better name. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <68d9f787d8c4fc8d1dbc227d6902fe801e42dea9.1736945236.git.mchehab+huawei@kernel.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15acpi/ghes: Change the type for source_idMauro Carvalho Chehab1-1/+1
As described at: ACPI 6.5 spec at: 18.3.2. ACPI Error Source In particular at GHES/GHESv2 table: Table 18.10 Generic Hardware Error Source Structure HEST source ID is actually a 16-bit value. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <0e83ba548c1aedd1299fe387b94db78986590a34.1736945236.git.mchehab+huawei@kernel.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15acpi/ghes: Fix acpi_ghes_record_errors() argumentMauro Carvalho Chehab1-1/+1
Align the header file with the actual implementation of this function, as the first argument is source ID and not notification type. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <d55f2a6ede5a168e42a20a228b2c066cb4c60939.1736945236.git.mchehab+huawei@kernel.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15acpi/ghes: simplify the per-arch caller to build HEST tableMauro Carvalho Chehab1-2/+2
The GHES driver requires not only a HEST table, but also a separate firmware file to store Error Structure records. It can't do one without the other. Simplify the caller logic for it to require one function. No functional changes. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <9584bb8953385e165681d5d185c503f8df8ef42f.1736945236.git.mchehab+huawei@kernel.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVEDMauro Carvalho Chehab1-1/+2
This is just duplicating ACPI_GHES_ERROR_SOURCE_COUNT, which has a better name. So, drop the duplication. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <9012bf4c9630adf15a22af3c88fda8270916887b.1736945236.git.mchehab+huawei@kernel.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15tests/qtest: Add intel-iommu testZhenzhong Duan1-0/+1
Add the framework to test the intel-iommu device. Currently only tested cap/ecap bits correctness when x-flts=on in scalable mode. Also tested cap/ecap bits consistency before and after system reset. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-21-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Introduce a property to control FS1GP cap bit settingZhenzhong Duan1-0/+1
This gives user flexibility to turn off FS1GP for debug purpose. It is also useful for future nesting feature. When host IOMMU doesn't support FS1GP but vIOMMU does, nested page table on host side works after turning FS1GP off in vIOMMU. This property has no effect when vIOMMU is in legacy mode or x-flts=off in scalable modme. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-20-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2Zhenzhong Duan1-1/+1
According to VTD spec, stage-1 page table could support 4-level and 5-level paging. However, 5-level paging translation emulation is unsupported yet. That means the only supported value for aw_bits is 48. So default aw_bits to 48 when stage-1 translation is turned on. For legacy and scalable modes, 48 is the default choice for modern OS when both 48 and 39 are supported. So it makes sense to set default to 48 for these two modes too starting from QEMU 9.2. Use pc_compat_9_1 to handle the compatibility for machines before 9.2. Suggested-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20241212083757.605022-17-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Flush stage-1 cache in iotlb invalidationZhenzhong Duan1-0/+1
According to spec, Page-Selective-within-Domain Invalidation (11b): 1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through (PGTT=100b) mappings associated with the specified domain-id and the input-address range are invalidated. 2. IOTLB entries caching first-stage (PGTT=001b) or nested (PGTT=011b) mapping associated with specified domain-id are invalidated. So per spec definition the Page-Selective-within-Domain Invalidation needs to flush first stage and nested cached IOTLB entries as well. We don't support nested yet and pass-through mapping is never cached, so what in iotlb cache are only first-stage and second-stage mappings. Add a tag pgtt in VTDIOTLBEntry to mark PGTT type of the mapping and invalidate entries based on PGTT type. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Message-Id: <20241212083757.605022-11-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Rename slpte to pteYi Liu1-1/+1
Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translation, rename variable and functions from slpte to pte whenever possible. But some are SST only, they are renamed with sl_ prefix. Signed-off-by: Yi Liu <yi.l.liu@intel.com> Co-developed-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Message-Id: <20241212083757.605022-6-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15intel_iommu: Add a placeholder variable for scalable mode stage-1 translationZhenzhong Duan1-0/+1
Add an new element flts in IntelIOMMUState to mark stage-1 translation support in scalable mode, this element will be exposed as an intel_iommu property x-flts finally. For now, it's only a placehholder and used for address width compatibility check and block host device passthrough until nesting is supported. Signed-off-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Message-Id: <20241212083757.605022-4-zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15virtio-gpu: Add definition for resource_uuid featureDorinda Bassey1-0/+3
Add the VIRTIO_GPU_F_RESOURCE_UUID feature to enable the assignment of resources UUIDs for export to other virtio devices. Signed-off-by: Dorinda Bassey <dbassey@redhat.com> Message-Id: <20241007070013.3350752-1-dbassey@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-01-15xen: do not use '%ms' scanf specifierRoger Pau Monne1-0/+1
The 'm' parameter used to request auto-allocation of the destination variable is not supported on FreeBSD, and as such leads to failures to parse. What's more, the current usage of '%ms' with xs_node_scanf() is pointless, as it just leads to a double allocation of the same string. Instead use xs_node_read() to read the whole xenstore node. Fixes: a783f8ad4ec9 ('xen: add a mechanism to automatically create XenDevice-s...') Fixes: 9b7737469080 ('hw/xen: update Xen console to XenDevice model') Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
2025-01-15hw/xen: Add xs_node_read() helper functionDavid Woodhouse1-0/+9
This returns the full contents of the node, having created the node path from the printf-style format string provided in its arguments. This will save various callers from having to do so for themselves (and from using xs_node_scanf() with the non-portable %ms format string. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> [remove double newline and constify trace parameters] Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
generated by cgit v1.1 at 2025-09-20 22:10:09 +0000