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2025-02-25hw/arm/fsl-imx8mp: Add on-chip RAMBernhard Beschow1-0/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-18-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add USB supportBernhard Beschow1-0/+12
Split the USB MMIO regions to better keep track of the implemented vs. unimplemented regions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-16-shentey@gmail.com [PMM: drop "static const" from usb_table for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add Ethernet controllerBernhard Beschow1-0/+8
The i.MX 8M Plus SoC actually has two ethernet controllers, the usual ENET one and a Designware one. There is no device model for the latter, so only add the ENET one. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-15-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Implement general purpose timersBernhard Beschow2-0/+12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-14-shentey@gmail.com [PMM: drop static const from gpt_attrs for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add watchdog supportBernhard Beschow1-0/+7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-13-shentey@gmail.com [PMM: drop static const from wdog_table for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add SPI controllersBernhard Beschow1-0/+8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-12-shentey@gmail.com [PMM: drop static const from spi_table for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add I2C controllersBernhard Beschow1-0/+11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-11-shentey@gmail.com [PMM: drop static const from i2c_table for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add GPIO controllersBernhard Beschow1-0/+14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-10-shentey@gmail.com [PMM: drop static const from gpio_table for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add PCIe supportBernhard Beschow2-0/+38
Linux checks for the PLLs in the PHY to be locked, so implement a model emulating that. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-9-shentey@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add USDHC storage controllersBernhard Beschow1-0/+7
The USDHC emulation allows for running real-world images such as those generated by Buildroot. Convert the board documentation accordingly instead of running a Linux kernel with ephemeral storage. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-8-shentey@gmail.com [PMM: drop 'static const' from usdhc_table[] for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add SNVSBernhard Beschow1-0/+2
SNVS contains an RTC which allows Linux to deal correctly with time. This is particularly useful when handling persistent storage which will be done in the next patch. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-7-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Implement clock treeBernhard Beschow3-0/+115
Fixes quite a few stack traces during the Linux boot process. Also provides the clocks for devices added later, e.g. enet1. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-6-shentey@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm: Add i.MX 8M Plus EVK boardBernhard Beschow1-0/+189
As a first step, implement the bare minimum: CPUs, RAM, interrupt controller, serial. All other devices of the A53 memory map are represented as TYPE_UNIMPLEMENTED_DEVICE, i.e. the whole memory map is provided. This allows for running Linux without it crashing due to invalid memory accesses. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-5-shentey@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: drop 'static const' from serial_table[] definition to avoid compile failure on GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/pci-host/designware: Prevent device attachment on internal PCIe root busBernhard Beschow1-0/+7
On the real device, the PCIe root bus is only connected to a PCIe bridge and does not allow for direct attachment of devices. Doing so in QEMU results in no PCI devices being detected by Linux. Instead, PCI devices should plug into the secondary PCIe bus spawned by the internal PCIe bridge. Unfortunately, QEMU defaults to plugging devices into the PCIe root bus. To work around this, every PCI device created on the command line needs an extra `bus=dw-pcie` option which is error prone. Fix that by marking the PCIe root bus as full which makes QEMU decend into the child PCIe bus. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-3-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/usb/hcd-dwc3: Align global registers size with LinuxBernhard Beschow1-1/+1
While at it add missing GUSB2RHBCTL register as found in i.MX 8M Plus reference manual. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-2-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25i386/cpu: add has_caches flag to check smp_cache configurationAlireza Sanaee1-0/+3
Add has_caches flag to SMPCompatProps, which helps in avoiding extra checks for every single layer of caches in x86 (and ARM in future). Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Link: https://lore.kernel.org/r/20250110145115.1574345-6-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-02-25target/loongarch: Enable virtual extioi featureBibo Mao1-0/+9
Feature virtual extioi is loongArch virt machine property rather than vCPU property in qemu side. However it is vCPU property in KVM kernel side, here add loongArch virt machine property checking and enable virt extioi feature when vCPU is created. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-02-24hw/mips/boston: Support dumpdtb monitor commandsPeter Maydell1-3/+18
The boston machine doesn't set MachineState::fdt to the DTB blob that it has loaded or created, which means that the QMP/HMP dumpdtb monitor commands don't work. Setting MachineState::fdt is easy in the non-FIT codepath: we can simply do so immediately before loading the DTB into guest memory. The FIT codepath is a bit more awkward as currently the FIT loader throws away the memory that the FDT was in after it loads it into guest memory. So we add a void *pfdt argument to load_fit() for it to store the FDT pointer into. There is some readjustment required of the pointer handling in loader-fit.c, so that it applies 'const' only where it should (e.g. the data pointer we get back from fdt_getprop() is const, because it's into the middle of the input FDT data, but the pointer that fit_load_image_alloc() should not be const, because it's freshly allocated memory that the caller can change if it likes). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250206151214.2947842-5-peter.maydell@linaro.org
2025-02-24hw/openrisc: Support monitor dumpdtb commandPeter Maydell1-1/+2
The openrisc machines don't set MachineState::fdt to point to their DTB blob. This means that although the command line '-machine dumpdtb=file.dtb' option works, the equivalent QMP and HMP monitor commands do not, but instead produce the error "This machine doesn't have a FDT". Set MachineState::fdt in openrisc_load_fdt(), when we write it to guest memory. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250206151214.2947842-3-peter.maydell@linaro.org
2025-02-22Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi3-6/+11
into staging virtio,pc,pci: features, fixes, cleanups Features: SR-IOV emulation for pci virtio-mem-pci support for s390 interleave support for cxl big endian support for vdpa svq new QAPI events for vhost-user Also vIOMMU reset order fixups are in. Fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAme4b8sPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpHKcIAKPJsVqPdda2dJ7b7FdyRT0Q+uwezXqaGHd4 # 7Lzih1wsxYNkwIAyPtEb76/21qiS7BluqlUCfCB66R9xWjP5/KfvAFj4/r4AEduE # fxAgYzotNpv55zcRbcflMyvQ42WGiZZHC+o5Lp7vDXUP3pIyHrl0Ydh5WmcD+hwS # BjXvda58TirQpPJ7rUL+sSfLih17zQkkDcfv5/AgorDy1wK09RBKwMx/gq7wG8yJ # twy8eBY2CmfmFD7eTM+EKqBD2T0kwLEeLfS/F/tl5Fyg6lAiYgYtCbGLpAmWErsg # XZvfZmwqL7CNzWexGvPFnnLyqwC33WUP0k0kT88Y5wh3/h98blw= # =tej8 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 21 Feb 2025 20:21:31 HKT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (41 commits) docs/devel/reset: Document reset expectations for DMA and IOMMU hw/vfio/common: Add a trace point in vfio_reset_handler hw/arm/smmuv3: Move reset to exit phase hw/i386/intel-iommu: Migrate to 3-phase reset hw/virtio/virtio-iommu: Migrate to 3-phase reset vhost-user-snd: correct the calculation of config_size net: vhost-user: add QAPI events to report connection state hw/virtio/virtio-nsm: Respond with correct length vdpa: Fix endian bugs in shadow virtqueue MAINTAINERS: add more files to `vhost` cryptodev/vhost: allocate CryptoDevBackendVhost using g_mem0() vhost-iova-tree: Update documentation vhost-iova-tree, svq: Implement GPA->IOVA & partial IOVA->HVA trees vhost-iova-tree: Implement an IOVA-only tree amd_iommu: Use correct bitmask to set capability BAR amd_iommu: Use correct DTE field for interrupt passthrough hw/virtio: reset virtio balloon stats on machine reset mem/cxl_type3: support 3, 6, 12 and 16 interleave ways hw/mem/cxl_type3: Ensure errp is set on realization failure hw/mem/cxl_type3: Fix special_ops memory leak on msix_init_exclusive_bar() failure ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-02-21hw/virtio: reset virtio balloon stats on machine resetDaniel P. Berrangé1-0/+4
When a machine is first booted, all virtio balloon stats are initialized to their default value -1 (18446744073709551615 when represented as unsigned). They remain that way while the firmware is loading, and early phase of guest OS boot, until the virtio-balloon driver is activated. Thereafter the reported stats reflect the guest OS activity. When a machine reset is performed, however, the virtio-balloon stats are left unchanged by QEMU, despite the guest OS no longer updating them, nor indeed even still existing. IOW, the mgmt app keeps getting stale stats until the guest OS starts once more and loads the virtio-balloon driver (if ever). At that point the app will see a discontinuity in the reported values as they sudden jump from the stale value to the new value. This jump is indigituishable from a valid data update. While there is an "last-updated" field to report on the freshness of the stats, that does not unambiguously tell the mgmt app whether the stats are still conceptually relevant to the current running workload. It is more conceptually useful to reset the stats to their default values on machine reset, given that the previous guest workload the stats reflect no longer exists. The mgmt app can now clearly identify that there are is no stats information available from the current executing workload. The 'last-updated' time is also reset back to 0. IOW, on every machine reset, the virtio stats are in the same clean state they were when the macine first powered on. A functional test is added to validate this behaviour with a real world guest OS. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20250204094202.2183262-1-berrange@redhat.com> Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-02-21hw/cxl: Introduce CXL_T3_MSIX_VECTOR enumerationLi Zhijian1-2/+2
Introduce the `CXL_T3_MSIX_VECTOR` enumeration to specify MSIX vector assignments specific to the Type 3 (T3) CXL device. The primary goal of this change is to encapsulate the MSIX vector uses that are unique to the T3 device within an enumeration, improving code readability and maintenance by avoiding magic numbers. This organizational change allows for more explicit references to each vector’s role, thereby reducing the potential for misconfiguration. It also modified `mailbox_reg_init_common` to accept the `msi_n` parameter, reflecting the new MSIX vector setup. This pertains to the T3 device privately; other endpoints should refrain from using it, despite its public accessibility to all of them. Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20250203161908.145406-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-02-20pcie_sriov: Register VFs after migrationAkihiko Odaki1-0/+2
pcie_sriov doesn't have code to restore its state after migration, but igb, which uses pcie_sriov, naively claimed its migration capability. Add code to register VFs after migration and fix igb migration. Fixes: 3a977deebe6b ("Intrdocue igb device emulation") Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20250116-reuse-v20-11-7cb370606368@daynix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-02-20pcie_sriov: Remove num_vfs from PCIESriovPFAkihiko Odaki1-1/+0
num_vfs is not migrated so use PCI_SRIOV_CTRL_VFE and PCI_SRIOV_NUM_VF instead. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20250116-reuse-v20-10-7cb370606368@daynix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-02-20pcie_sriov: Reuse SR-IOV VF device instancesAkihiko Odaki1-1/+0
Disable SR-IOV VF devices by reusing code to power down PCI devices instead of removing them when the guest requests to disable VFs. This allows to realize devices and report VF realization errors at PF realization time. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20250116-reuse-v20-8-7cb370606368@daynix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-02-20pcie_sriov: Ensure VF addr does not overflowAkihiko Odaki1-2/+3
pci_new() aborts when creating a VF with addr >= PCI_DEVFN_MAX. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20250116-reuse-v20-7-7cb370606368@daynix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-02-20hw/arm: Add NPCM845 Evaluation boardHao Wu1-0/+21
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-17-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-20hw/arm: Add NPCM8XX SoCHao Wu1-0/+106
Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250219184609.1839281-16-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-20hw/net: Add NPCM8XX PCS ModuleHao Wu1-0/+42
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII PHY. This implementation contains all the default registers and the soft reset feature that are required to load the Linux kernel driver. Further features have not been implemented yet. Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250219184609.1839281-15-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-20hw/misc: Support NPCM8XX CLK Module RegistersHao Wu1-2/+8
NPCM8XX adds a few new registers and have a different set of reset values to the CLK modules. This patch supports them. This patch doesn't support the new clock values generated by these registers. Currently no modules use these new clock values so they are not necessary at this point. Implementation of these clocks might be required when implementing these modules. Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-14-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-20hw/misc: Add nr_regs and cold_reset_values to NPCM CLKHao Wu1-1/+8
These 2 values are different between NPCM7XX and NPCM8XX CLKs. So we add them to the class and assign different values to them. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-13-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-20hw/misc: Move NPCM7XX CLK to NPCM CLKHao Wu2-11/+13
A lot of NPCM7XX and NPCM8XX CLK modules share the same code, this commit moves the NPCM7XX CLK to NPCM CLK for these properties. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-12-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-20hw/misc: Rename npcm7xx_clk to npcm_clkHao Wu2-4/+4
NPCM7XX and NPCM8XX have a different set of CLK registers. This commit changes the name of the clk files to be used by both NPCM7XX and NPCM8XX CLK modules. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-11-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-20hw/misc: Store DRAM size in NPCM8XX GCR ModuleHao Wu1-0/+1
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR module. Since we don't simulate a detailed memory controller, we need to store this information directly similar to the NPCM7XX's INCTR3 register. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-9-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-20hw/misc: Add support for NPCM8XX GCRHao Wu1-2/+4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-8-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-20hw/misc: Add nr_regs and cold_reset_values to NPCM GCRHao Wu1-2/+11
These 2 values are different between NPCM7XX and NPCM8XX GCRs. So we add them to the class and assign different values to them. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-7-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-20hw/misc: Move NPCM7XX GCR to NPCM GCRHao Wu2-4/+5
A lot of NPCM7XX and NPCM8XX GCR modules share the same code, this commit moves the NPCM7XX GCR to NPCM GCR for these properties. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-6-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-20hw/misc: Rename npcm7xx_gcr to npcm_gcrHao Wu2-4/+4
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module needs to fit both. This commit changes the name of the GCR module. Future commits will add the support for NPCM8XX GCRs. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-5-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-20hw/ssi: Make flash size a property in NPCM7XX FIUHao Wu1-0/+1
This allows different FIUs to have different flash sizes, useful in NPCM8XX which has multiple different sized FIU modules. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-id: 20250219184609.1839281-4-wuhaotsh@google.com [PMM: flash_size must be a uint64_t to build on 32-bit hosts] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-16hw/qdev-properties-system: Introduce EndianMode QAPI enumPhilippe Mathieu-Daudé1-0/+7
Introduce the EndianMode type and the DEFINE_PROP_ENDIAN() macros. Endianness can be BIG, LITTLE or unspecified (default). Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250213122217.62654-2-philmd@linaro.org>
2025-02-16hw/boards: Rename no_sdcard -> auto_create_sdcardPhilippe Mathieu-Daudé1-1/+1
Invert the 'no_sdcard' logic, renaming it as the more explicit "auto_create_sdcard". Machines are supposed to create a SD Card drive when this flag is set. In many cases it doesn't make much sense (as boards don't expose SD Card host controller), but this is patch only aims to expose that nonsense; so no logical change intended (mechanical patch using gsed). Most of the changes are: - mc->no_sdcard = ON_OFF_AUTO_OFF; + mc->auto_create_sdcard = true; Except in . hw/core/null-machine.c . hw/arm/xilinx_zynq.c . hw/s390x/s390-virtio-ccw.c where the disabled option is manually removed (since default): - mc->no_sdcard = ON_OFF_AUTO_ON; + mc->auto_create_sdcard = false; - mc->auto_create_sdcard = false; and in system/vl.c we change the 'default_sdcard' type to boolean. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250204200934.65279-4-philmd@linaro.org>
2025-02-16hw/boards: Convert no_sdcard flag to OnOffAuto tri-statePhilippe Mathieu-Daudé1-1/+1
MachineClass::no_sdcard is initialized as false by default. To catch all uses, convert it to a tri-state, having the current default (false) becoming AUTO. No logical change intended. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250204200934.65279-2-philmd@linaro.org>
2025-02-16hw/xen: Have legacy Xen backend inherit from DYNAMIC_SYS_BUS_DEVICEPhilippe Mathieu-Daudé1-2/+3
Because the legacy Xen backend devices can optionally be plugged on the TYPE_PLATFORM_BUS_DEVICE, have it inherit TYPE_DYNAMIC_SYS_BUS_DEVICE. Remove the implicit TYPE_XENSYSDEV instance_size. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alexander Graf <graf@amazon.com> Tested-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20250125181343.59151-10-philmd@linaro.org>
2025-02-16hw/sysbus: Introduce TYPE_DYNAMIC_SYS_BUS_DEVICEPhilippe Mathieu-Daudé1-0/+2
Some TYPE_SYS_BUS_DEVICEs can be optionally dynamically plugged on the TYPE_PLATFORM_BUS_DEVICE. Rather than sometimes noting that with comment around the 'user_creatable = true' line in each DeviceRealize handler, introduce an abstract TYPE_DYNAMIC_SYS_BUS_DEVICE class. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alexander Graf <graf@amazon.com> Reviewed-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250125181343.59151-4-philmd@linaro.org>
2025-02-13i386/fw_cfg: move hpet_cfg definition to hpet.cZhao Liu1-1/+1
HPET device needs to access and update hpet_cfg variable, but now it is defined in hw/i386/fw_cfg.c and Rust code can't access it. Move hpet_cfg definition to hpet.c (and rename it to hpet_fw_cfg). This allows Rust HPET device implements its own global hpet_fw_cfg variable, and will further reduce the use of unsafe C code access and calls in the Rust HPET implementation. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250210030051.2562726-2-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-02-12Merge tag 'pull-loongarch-20250212' of https://gitlab.com/bibo-mao/qemu into ↵Stefan Hajnoczi1-1/+4
staging loongarch queue # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCZ6wQngAKCRAfewwSUazn # 0SggAQDk5mp90dBJwu05kioq+Inx/bwxmamweA+FmeqAnoQ79QEApDBPfppkrN2y # AxNZL0EL5zRFU3zECSTevpRMQ3UoVQk= # =tLFD # -----END PGP SIGNATURE----- # gpg: Signature made Tue 11 Feb 2025 22:08:14 EST # gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1 # gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C # Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1 * tag 'pull-loongarch-20250212' of https://gitlab.com/bibo-mao/qemu: hw/loongarch/virt: CPU irq line connection improvement hw/loongarch/virt: Remove unused ipistate hw/loongarch/virt: Set iocsr address space when CPU is created hw/loongarch/virt: Add separate file for fdt building hw/loongarch/virt: Rename function prefix name hw/loongarch/virt: Rename filename acpi-build with virt-acpi-build Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-02-12hw/loongarch/virt: CPU irq line connection improvementBibo Mao1-0/+2
Interrupt controller extioi and ipi connect to CPU with irq line method. With command -smp x, -device la464-loongarch-cpu, smp.cpus is not accurate for all possible CPU objects, possible_cpu_arch_ids() is used. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-02-12hw/loongarch/virt: Add separate file for fdt buildingBibo Mao1-0/+1
Similiar with virt-acpi-build.c, file virt-fdt-build.c is added here. And move functions relative with fdt table building to the file. It is only code movement and there is no function change. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-02-12hw/loongarch/virt: Rename function prefix nameBibo Mao1-1/+1
Replace function prefix name loongarch_xxx with virt_xxx in file virt-acpi-build.c Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-02-11vfio: Introduce vfio_get_vfio_device()Cédric Le Goater1-0/+1
This helper will be useful in the listener handlers to extract the VFIO device from a memory region using memory_region_owner(). At the moment, we only care for PCI passthrough devices. If the need arises, we will add more. Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250206131438.1505542-5-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
generated by cgit v1.1 at 2025-09-20 13:10:00 +0000