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2025-05-30hw/i386/x86: Remove X86MachineClass::save_tsc_khz fieldPhilippe Mathieu-Daudé1-5/+0
The X86MachineClass::save_tsc_khz boolean was only used by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got removed. Remove it and simplify tsc_khz_needed(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-11-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-30hw/i386/pc: Remove deprecated pc-q35-2.5 and pc-i440fx-2.5 machinesPhilippe Mathieu-Daudé1-3/+0
These machines has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") they can now be removed. Remove the now unused empty pc_compat_2_5[] array. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-10-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-30hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_DISABLE_PCIE definitionPhilippe Mathieu-Daudé1-4/+0
VIRTIO_PCI_FLAG_DISABLE_PCIE was only used by the hw_compat_2_4[] array, via the 'x-disable-pcie=false' property. We removed all machines using that array, lets remove all the code around VIRTIO_PCI_FLAG_DISABLE_PCIE (see commit 9a4c0e220d8 for similar VIRTIO_PCI_FLAG_* enum removal). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-9-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-30hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_MIGRATE_EXTRA definitionPhilippe Mathieu-Daudé1-4/+0
VIRTIO_PCI_FLAG_MIGRATE_EXTRA was only used by the hw_compat_2_4[] array, via the 'migrate-extra=true' property. We removed all machines using that array, lets remove all the code around VIRTIO_PCI_FLAG_MIGRATE_EXTRA. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-ID: <20250512083948.39294-8-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-30hw/core/machine: Remove hw_compat_2_4[] arrayPhilippe Mathieu-Daudé1-3/+0
The hw_compat_2_4[] array was only used by the pc-q35-2.4 and pc-i440fx-2.4 machines, which got removed. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-6-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-30hw/i386/pc: Remove pc_compat_2_4[] arrayPhilippe Mathieu-Daudé1-3/+0
The pc_compat_2_4[] array was only used by the pc-q35-2.4 and pc-i440fx-2.4 machines, which got removed. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-4-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-30hw/i386/pc: Remove PCMachineClass::broken_reserved_end fieldPhilippe Mathieu-Daudé1-1/+0
The PCMachineClass::broken_reserved_end field was only used by the pc-q35-2.4 and pc-i440fx-2.4 machines, which got removed. Remove it and simplify pc_memory_init(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-3-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-29hw/block: Drop unused nand.cPeter Maydell1-18/+0
The nand.c device (TYPE_NAND) is an emulation of a NAND flash memory chip which was used by the old OMAP boards. No current QEMU board uses it, and although techically "-device nand,chip-id=0x6b" doesn't error out, it's not possible to usefully use it from the command line because the only interface it has is via calling C functions like nand_setpins() and nand_setio(). The "config OMAP" stanza (used only by the SX1 board) is the only thing that does "select NAND" to compile in this code, but the SX1 board doesn't actually use the NAND device. Remove the NAND device code entirely; this is effectively leftover cleanup from when we dropped the PXA boards and the OMAP boards other than the sx1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250522142859.3122389-1-peter.maydell@linaro.org
2025-05-29hw/arm: Add GMAC devices to NPCM8XX SoCHao Wu1-1/+4
The GMAC was originally created for the 8xx machine. During upstreaming both the GMAC and the 8XX we removed it so they would not depend on each other for the process, that connection should be added back in. Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Nabih Estefan <nabihestefan@google.com> Message-id: 20250508220718.735415-2-nabihestefan@google.com Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-28i386/tdx: Track mem_ptr for each firmware entry of TDVFXiaoyao Li1-0/+7
For each TDVF sections, QEMU needs to copy the content to guest private memory via KVM API (KVM_TDX_INIT_MEM_REGION). Introduce a field @mem_ptr for TdxFirmwareEntry to track the memory pointer of each TDVF sections. So that QEMU can add/copy them to guest private memory later. TDVF sections can be classified into two groups: - Firmware itself, e.g., TDVF BFV and CFV, that located separately from guest RAM. Its memory pointer is the bios pointer. - Sections located at guest RAM, e.g., TEMP_MEM and TD_HOB. mmap a new memory range for them. Register a machine_init_done callback to do the stuff. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250508150002.689633-21-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-28i386/tdvf: Introduce function to parse TDVF metadataIsaku Yamahata1-0/+38
TDX VM needs to boot with its specialized firmware, Trusted Domain Virtual Firmware (TDVF). QEMU needs to parse TDVF and map it in TD guest memory prior to running the TDX VM. A TDVF Metadata in TDVF image describes the structure of firmware. QEMU refers to it to setup memory for TDVF. Introduce function tdvf_parse_metadata() to parse the metadata from TDVF image and store the info of each TDVF section. TDX metadata is located by a TDX metadata offset block, which is a GUID-ed structure. The data portion of the GUID structure contains only an 4-byte field that is the offset of TDX metadata to the end of firmware file. Select X86_FW_OVMF when TDX is enable to leverage existing functions to parse and search OVMF's GUID-ed structures. Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Co-developed-by: Xiaoyao Li <xiaoyao.li@intel.com> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250508150002.689633-18-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-28qapi: make s390x specific CPU commands unconditionally availableDaniel P. Berrangé1-1/+1
This removes the TARGET_S390X and CONFIG_KVM conditions from the CPU commands that are conceptually specific to s390x. Top level stubs are provided to cope with non-s390x targets, or builds without KVM. The removal of CONFIG_KVM is justified by the fact there is no conceptual difference between running 'qemu-system-s390x -accel tcg' on a build with and without KVM built-in, so apps only using TCG can't rely on the CONFIG_KVM in the schema. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-11-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-25hw/misc/aspeed_hace: Support DMA 64 bits dram addressJamin Lin1-0/+1
According to the AST2700 design, the data source address is 64-bit, with R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0]. Similarly, the digest address is 64-bit, with R_HASH_DEST_HI storing bits [63:32] and R_HASH_DEST storing bits [31:0]. To maintain compatibility with older SoCs such as the AST2600, the AST2700 HW automatically set bit 34 of the 64-bit sg_addr. As a result, the firmware only needs to provide a 32-bit sg_addr containing bits [31:0]. This is sufficient for the AST2700, as it uses a DRAM offset rather than a DRAM address. Introduce a has_dma64 class attribute and set it to true for the AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-15-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-25hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit addressesJamin Lin1-0/+3
According to the AST2700 design, the data source address is 64-bit, with R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0]. Similarly, the digest address is 64-bit, with R_HASH_DIGEST_HI storing bits [63:32] and R_HASH_DIGEST storing bits [31:0]. The HMAC key buffer address is also 64-bit, with R_HASH_KEY_BUFF_HI storing bits [63:32] and R_HASH_KEY_BUFF storing bits [31:0]. The AST2700 supports a maximum DRAM size of 8 GB, with a DRAM addressable range from 0x0_0000_0000 to 0x1_FFFF_FFFF. Since this range fits within 34 bits, only bits [33:0] are needed to store the DRAM offset. To optimize address storage, the high physical address bits [1:0] of the source, digest and key buffer addresses are stored as dram_offset bits [33:32]. To achieve this, a src_hi_mask with a mask value of 0x3 is introduced, ensuring that src_addr_hi consists of bits [1:0]. The final src_addr is computed as (src_addr_hi[1:0] << 32) | src_addr[31:0], representing the DRAM offset within bits [33:0]. Similarly, a dest_hi_mask with a mask value of 0x3 is introduced to ensure that dest_addr_hi consists of bits [1:0]. The final dest_addr is calculated as (dest_addr_hi[1:0] << 32) | dest_addr[31:0], representing the DRAM offset within bits [33:0]. Additionally, a key_hi_mask with a mask value of 0x3 is introduced to ensure that key_buf_addr_hi consists of bits [1:0]. The final key_buf_addr is determined as (key_buf_addr_hi[1:0] << 32) | key_buf_addr[31:0], representing the DRAM offset within bits [33:0]. This approach eliminates the need to reduce the high part of the DRAM physical address for DMA operations. Previously, this was calculated as (high physical address bits [7:0] - 4), since the DRAM start address is 0x4_00000000, making the high part address [7:0] - 4. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-14-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-25hw/misc/aspeed_hace: Move register size to instance class and dynamically ↵Jamin Lin1-2/+3
allocate regs Dynamically allocate the register array by removing the hardcoded ASPEED_HACE_NR_REGS macro. To support different register sizes across SoC variants, introduce a new "nr_regs" class attribute and replace the static "regs" array with dynamically allocated memory. Add a new "aspeed_hace_unrealize" function to properly free the allocated "regs" memory during device cleanup. Remove the bounds checking in the MMIO read/write handlers since the MemoryRegion size now matches the (register array size << 2). This commit updates the VMState fields accordingly. The VMState version was already bumped in a previous patch of this series, so no further version change is needed. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-13-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-25hw/misc/aspeed_hace: Remove unused code for better readabilityJamin Lin1-2/+0
In the previous design of the hash framework, accumulative hashing was not supported. To work around this limitation, commit 5cd7d85 introduced an iov_cache array to store all the hash data from firmware. Once the ASPEED HACE model collected all the data, it passed the iov_cache to the hash API to calculate the final digest. However, with commit e3c0752, the hash framework now supports accumulative hashing. This allows us to refactor the ASPEED HACE model, removing redundant logic and simplifying the implementation for better readability and maintainability. As a result, the iov_count variable is no longer needed—it was previously used to track how many cached entries were used for hashing. To maintain VMSTATE compatibility after removing this field, the VMSTATE_VERSION is bumped to 2 This cleanup follows significant changes in commit 4c1d0af4a28d, making the model more readable. - Deleted "iov_cache" and "iov_count" from "AspeedHACEState". - Removed "reconstruct_iov" function and related logic. - Simplified "do_hash_operation" by eliminating redundant checks. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-20hw/pci-host: Remove unused pci_host_data_be_opsRakesh Jeyasingh2-5/+0
pci_host_data_be_ops became unused after endianness fixes Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Rakesh Jeyasingh <rakeshjb010@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Thomas Huth <thuth@redhat.com> Link: https://lore.kernel.org/r/20250429170354.150581-3-rakeshjb010@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-19hw/riscv: Configurable MPFS CLINT timebase freqSebastian Huber1-0/+1
This property enables the setting of the CLINT timebase frequency through the command line, for example: -machine microchip-icicle-kit,clint-timebase-frequency=10000000 Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250319061342.26435-6-sebastian.huber@embedded-brains.de> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-05-19hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structureSunil V L1-0/+1
When the IOMMU is implemented as a PCI device, its BDF is created locally in virt.c. However, the same BDF is also required in virt-acpi-build.c to support ACPI. Therefore, make this information part of the global RISCVVirtState structure so that it can be accessed outside of virt.c as well. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250322043139.2003479-2-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-05-15Merge tag 'pull-target-arm-20250515' of ↵Stefan Hajnoczi3-271/+271
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * target/arm: refactoring for compile-twice changes * MAINTAINERS: Add an entry for the Bananapi machine * arm/omap: remove hard coded tabs * rust: pl011: Cut down amount of text quoted from PL011 TRM * target/arm: refactor Arm CPU class hierarchy # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmglwIUZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3sclD/9AgQ5uDlN6gIRupx2PUHAt # liFvncSS/1hPHbf4h9A1WgN34EDaF8TuHi8eexSMMlHQpI5yFumd7UIYUDxpRqj4 # 13gYhBqbnV68S4tWB2g/kCcSNYSLmRQT/b+iwCBtwEJJrDFXlMYFWS50DDS/wxzl # sIbcEnixT9PfPh22e01Ib9jCILPzHEVzegMtn5dFl86nLCqQufycNExOvEOXTC9w # smCTNHGSIM4TFzKOQ7pNgaAFiqpYenwvPgYElqgGZdwpEB/vmFokXUauQzf2uwVH # Nx/361YWi8hQQkG/qEqzcu+J5PwydZssXCO2gEsQVUZMCK/g+naNAiFThMWv/zAu # gJ+MWghlSXqAEStLf/+D8w03+I+jChINNxip/F4pgAzbi8mPp/Te+u/G+ra6vD8W # AvWzvZwxbTLOlTOYzKsOGF7nq86A20hJBTfpm/Hlbd0ou80YQLO23Dxr4Wmbua5n # gbvUad88V5J9KeZUAg4wCyuMGii6X4rezJVL55hE+PIrPRi3q4TXBjk7KG29SkA1 # UCbXm8EGiBMCAE04u6dWkcd8003RbgAfrAK0b9VGUEcEXO1O//ivlWJw/TQWf8pn # V1UOiXocmXOI5vyy01gjz2iDv8ty/4jSGPzCQ80ijl58Gmm8fmDRxuWPLtDS0lBS # QcFEV2oIUjMEEpsCYV07KQ== # =MECx # -----END PGP SIGNATURE----- # gpg: Signature made Thu 15 May 2025 06:23:01 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250515' of https://git.linaro.org/people/pmaydell/qemu-arm: (58 commits) target/arm/tcg/vfp_helper: compile file twice (system, user) target/arm/tcg/arith_helper: compile file once target/arm/tcg/tlb-insns: compile file once (system) target/arm/helper: restrict define_tlb_insn_regs to system target target/arm/tcg/tlb_helper: compile file twice (system, user) target/arm/tcg/neon_helper: compile file twice (system, user) target/arm/tcg/iwmmxt_helper: compile file twice (system, user) target/arm/tcg/hflags: compile file twice (system, user) target/arm/tcg/crypto_helper: compile file once target/arm/tcg/vec_internal: use forward declaration for CPUARMState target/arm/machine: compile file once (system) target/arm/kvm-stub: add missing stubs target/arm/machine: move cpu_post_load kvm bits to kvm_arm_cpu_post_load function target/arm/machine: remove TARGET_AARCH64 from migration state target/arm/machine: reduce migration include to avoid target specific definitions target/arm/kvm-stub: compile file once (system) target/arm/meson: accelerator files are not needed in user mode target/arm/ptw: compile file once (system) target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw target/arm/ptw: replace target_ulong with int64_t ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-15Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi9-7/+59
into staging virtio,pci,pc: fixes, features vhost-scsi now supports scsi hotplug cxl gained a bag of new operations, motably media operations virtio-net now supports SR-IOV emulation pci-testdev now supports backing memory bar with host memory amd iommu now supports migration fixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCgAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmgkg0UPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpcDIH+wbrq7DzG+BVOraYtmD69BQCzYszby1mAWry # 2OUYuAx9Oh+DsAwbzwbBdh9+SmJoi1oJ/d8rzSK328hdDrpCaPmc7bcBdAWJ3YcB # bGNPyJ+9eJLRXtlceGIhfAOMLIB0ugXGkHLQ61zlVCTg4Xwnj7/dQp2tAQ1BkTwW # Azc7ujBoJOBF3WVpa1Pqw0t1m3K74bwanOlkIg/JUWXk27sgP2YMnyrcpOu9Iz1T # VazgobyHo5y15V0wvd05w4Bk7cJSHwgW+y3DtgTtIffetIaAbSRgl3Pl5Ic1yKcX # ofg9aDFN6m0S8tv4WgFc+rT3Xaa/aPue9awjD5sEEldRasWKKNo= # =847R # -----END PGP SIGNATURE----- # gpg: Signature made Wed 14 May 2025 07:49:25 EDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (27 commits) hw/i386/amd_iommu: Allow migration when explicitly create the AMDVI-PCI device hw/i386/amd_iommu: Isolate AMDVI-PCI from amd-iommu device to allow full control over the PCI device creation intel_iommu: Take locks when looking for and creating address spaces intel_iommu: Use BQL_LOCK_GUARD to manage cleanup automatically virtio: Move virtio_reset() virtio: Call set_features during reset vhost-scsi: support VIRTIO_SCSI_F_HOTPLUG vhost-user: return failure if backend crash when live migration vhost: return failure if stop virtqueue failed in vhost_dev_stop system/runstate: add VM state change cb with return value pci-testdev.c: Add membar-backed option for backing membar pcie_sriov: Make a PCI device with user-created VF ARI-capable docs: Document composable SR-IOV device virtio-net: Implement SR-IOV VF virtio-pci: Implement SR-IOV PF pcie_sriov: Allow user to create SR-IOV device pcie_sriov: Check PCI Express for SR-IOV PF pcie_sriov: Ensure PF and VF are mutually exclusive hw/pci: Fix SR-IOV VF number calculation hw/pci: Do not add ROM BAR for SR-IOV VF ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-15Merge tag 'pull-request-2025-05-14' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi2-5/+0
staging * Removal of obsolete s390x machines * Fix a memleak in s390x code * Skip some functional tests if the corresponding feature is not available # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmgkfWURHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbXaKA/+K/buSKZWNcvrXtU4AqEyIjicvUsbY79S # BGmwTjO46uDzlqTIOxGJ2uBAocXSlNJ7YsvH75vBHWHF3Vy6LB1zPWDgaYTz7XkA # K9GqtrmRdlPArKa1Q7ot0tJ/wu7lzQuccieJJwNJhotMC3C4dl1HSpp+u/rmk7gG # vG9l5Cdi34BWXp2QCKPdrNs++4mOudLSJtYhBlSpxIaBe6h2LoHmKJNEmD9x4Xcg # SWTqalpWUhJW4L3zCj1JXWv6HAyR6GG7+7FLr5FkorSDG/sMX7+09GLE1/BLlD87 # KtZlTBkcbXs+eXmP4y+qtskI0ca4dLaZnfIq8/v0wqCXvfOUM4Xi0E2HvGmHeI4u # rvC/ZhK2RztMZbVMFXHSmCFJvpi2sGgH+sIHt18BJzkAC+nx0ZdCz81fgKVERHhJ # 1ZnsRiMcf7dI6yEgbJ89vZihv3WbyCcwlnyLDN+lovZzCYTvxPLn5SRH0LEm4kN5 # N/qRwTTlPM4xCGCSc3JEGJVDDy36ojVfvGMFt4ZcFehcpkfcLznw7QYjk3QDwI2N # 58FImsf2VVEl4sdpzpi6zfutMhFuL1N0m/kXb8GBonekXYTPtyBMqHsmhyRe5xXN # vP9paghpU0xBuDMtmZWyq4RCubZNESA7wAbSf0+VcC/1Uhjc3QS5820kV7/WVwsU # VwObtSEAG1c= # =zUob # -----END PGP SIGNATURE----- # gpg: Signature made Wed 14 May 2025 07:24:21 EDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2025-05-14' of https://gitlab.com/thuth/qemu: tests/functional: Skip the screendump tests if the command is not available tests/functional/test_s390x_tuxrun: Check whether the machine is available include/hw/dma/xlnx_dpdma: Remove dependency on console.h s390x: Fix leak in machine_set_loadparm hw/s390x/s390-virtio-ccw: Remove the deprecated 4.0 machine type hw/s390x/s390-virtio-ccw: Remove the deprecated 3.1 machine type hw/s390x: Remove the obsolete hpage_1m_allowed switch hw/s390x/s390-virtio-ccw: Remove the deprecated 3.0 machine type hw/s390x/s390-virtio-ccw: Remove the deprecated 2.12 machine type target/s390x: Rename the qemu_V2_11 feature set to qemu_MIN hw/s390x/event-facility: Remove the obsolete "allow_all_mask_sizes" code hw/s390x/s390-virtio-ccw: Remove the deprecated 2.11 machine type hw/s390x/s390-virtio-ccw: Remove the deprecated 2.10 machine type Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-14hw/arm: Replace TABs for spaces in OMAP board and device codeSantiago Monserrat Campanello3-271/+271
In hw/arm and include/hw/arm, some source files for the OMAP SoC and the sx1 boards that are our only remaining OMAP boards still have hard-coded tabs (almost entirely used for the indent on inline comments, not for actual code indent). Replace the tabs with spaces using vim :retab. I used 4 spaces except in some defines and comments where I tried to put everything aligned in the same column for better readability. This commit is a purely whitespace-only change. Signed-off-by: Santiago Monserrat Campanello <santimonserr@gmail.com> Message-id: 20250505131130.82206-1-santimonserr@gmail.com Resolves: https://gitlab.com/qemu-project/qemu/-/issues/373 [PMM: expanded commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14include/hw/dma/xlnx_dpdma: Remove dependency on console.hThomas Huth1-1/+0
console.h brings a dependency on the <epoxy/opengl.h> and the pixman header file (if available), so we should avoid to include this file if it is not really necessary. console.h does not seem to be necessary for the xlnx_dpdma code, so drop the include here. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250508144120.163009-2-thuth@redhat.com>
2025-05-14vhost-user: return failure if backend crash when live migrationHaoqian He3-3/+3
Live migration should be terminated if the vhost-user backend crashes before the migration completes. Specifically, since the vhost device will be stopped when VM is stopped before the end of the live migration, in current implementation if the backend crashes, vhost-user device set_status() won't return failure, live migration won't perceive the disconnection between QEMU and the backend. When the VM is migrated to the destination, the inflight IO will be resubmitted, and if the IO was completed out of order before, it will cause IO error. To fix this issue: 1. Add the return value to set_status() for VirtioDeviceClass. a. For the vhost-user device, return failure when the backend crashes. b. For other virtio devices, always return 0. 2. Return failure if vhost_dev_stop() failed for vhost-user device. If QEMU loses connection with the vhost-user backend, virtio set_status() can return failure to the upper layer, migration_completion() can handle the error, terminate the live migration, and restore the VM, so that inflight IO can be completed normally. Signed-off-by: Haoqian He <haoqian.he@smartx.com> Message-Id: <20250416024729.3289157-4-haoqian.he@smartx.com> Tested-by: Lei Yang <leiyang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-05-14vhost: return failure if stop virtqueue failed in vhost_dev_stopHaoqian He1-3/+5
This patch captures the error of vhost_virtqueue_stop() in vhost_dev_stop() and returns the error upward. Specifically, if QEMU is disconnected from the vhost backend, some actions in vhost_dev_stop() will fail, such as sending vhost-user messages to the backend (GET_VRING_BASE, SET_VRING_ENABLE) and vhost_reset_status. Considering that both set_vring_enable and vhost_reset_status require setting the specific virtio feature bit, we can capture vhost_virtqueue_stop()'s error to indicate that QEMU has lost connection with the backend. This patch is the pre patch for 'vhost-user: return failure if backend crashes when live migration', which makes the live migration aware of the loss of connection with the vhost-user backend and aborts the live migration. Signed-off-by: Haoqian He <haoqian.he@smartx.com> Message-Id: <20250416024729.3289157-3-haoqian.he@smartx.com> Tested-by: Lei Yang <leiyang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-05-14pcie_sriov: Make a PCI device with user-created VF ARI-capableAkihiko Odaki1-2/+5
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20250314-sriov-v9-9-57dae8ae3ab5@daynix.com> Tested-by: Yui Washizu <yui.washidu@gmail.com> Tested-by: Pasha Tatashin <pasha.tatashin@soleen.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-05-14virtio-pci: Implement SR-IOV PFAkihiko Odaki1-0/+1
Allow user to attach SR-IOV VF to a virtio-pci PF. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20250314-sriov-v9-6-57dae8ae3ab5@daynix.com> Tested-by: Yui Washizu <yui.washidu@gmail.com> Tested-by: Pasha Tatashin <pasha.tatashin@soleen.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-05-14pcie_sriov: Allow user to create SR-IOV deviceAkihiko Odaki2-1/+23
A user can create a SR-IOV device by specifying the PF with the sriov-pf property of the VFs. The VFs must be added before the PF. A user-creatable VF must have PCIDeviceClass::sriov_vf_user_creatable set. Such a VF cannot refer to the PF because it is created before the PF. A PF that user-creatable VFs can be attached calls pcie_sriov_pf_init_from_user_created_vfs() during realization and pcie_sriov_pf_exit() when exiting. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20250314-sriov-v9-5-57dae8ae3ab5@daynix.com> Tested-by: Yui Washizu <yui.washidu@gmail.com> Tested-by: Pasha Tatashin <pasha.tatashin@soleen.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-05-14hw/cxl/cxl-mailbox-utils: CXL CCI Get/Set alert config commandsSweta Kumari1-0/+15
1) get alert configuration(Opcode 4201h) 2) set alert configuration(Opcode 4202h) Signed-off-by: Sweta Kumari <s5.kumari@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20250305092501.191929-7-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-05-14hw/cxl/cxl-mailbox-utils: Media operations Sanitize and Write Zeros commands ↵Vinayak Holikatti1-0/+4
CXL r3.2(8.2.10.9.5.3) CXL spec 3.2 section 8.2.10.9.5.3 describes media operations commands. CXL devices supports media operations Sanitize and Write zero command. Signed-off-by: Vinayak Holikatti <vinayak.kh@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20250305092501.191929-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-05-14hw/cxl: Support aborting background commandsDavidlohr Bueso2-0/+5
As of 3.1 spec, background commands can be canceled with a new abort command. Implement the support, which is advertised in the CEL. No ad-hoc context undoing is necessary as all the command logic of the running bg command is done upon completion. Arbitrarily, the on-going background cmd will not be aborted if already at least 85% done; A mutex is introduced to stabilize mbox request cancel command vs the timer callback being fired scenarios (as well as reading the mbox registers). While some operations under critical regions may be unnecessary (irq notifying, cmd callbacks), this is not a path where performance is important, so simplicity is preferred. Tested-by: Ajay Joshi <ajay.opensrc@micron.com> Reviewed-by: Ajay Joshi <ajay.opensrc@micron.com> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20250305092501.191929-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-05-14hw/intc/loongarch_pch: Merge three memory region into oneBibo Mao1-2/+0
Since memory region iomem supports memory access size with 1/2/4/8, it can be used for memory region iomem8 and iomem32_high. Now remove memory region iomem8 and iomem32_high, merge them into iomem together. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023754.1877445-5-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Rename memory region iomem32_low with iomemBibo Mao1-1/+1
Rename memory region iomem32_low with iomem, also change ops name as follows: loongarch_pch_pic_reg32_low_ops --> loongarch_pch_pic_ops loongarch_pch_pic_low_readw --> loongarch_pch_pic_read loongarch_pch_pic_low_writew --> loongarch_pch_pic_write Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023754.1877445-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Set version information at initial stageBibo Mao1-2/+15
Register PCH_PIC_INT_ID constains version and supported irq number information, and it is read only register. The detailed value can be set at initial stage, rather than read callback. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-5-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Remove some duplicate macroBibo Mao1-5/+0
The meaning of macro definition STATUS_LO_START is simliar with PCH_PIC_INT_STATUS, only that offset is different, the same for macro POL_LO_START. Now remove these duplicated macro definitions. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Modify register name PCH_PIC_xxx_OFFSET with PCH_PIC_xxxBibo Mao1-2/+2
Macro PCH_PIC_HTMSI_VEC_OFFSET and PCH_PIC_ROUTE_ENTRY_OFFSET is renamed as PCH_PIC_HTMSI_VEC and PCH_PIC_ROUTE_ENTRY separately, it is easier to understand. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Modify name of some registersBibo Mao1-18/+9
For some registers with width 8 bytes, its name is something like PCH_PIC_INT_ID_LO and PCH_PIC_INT_ID_HI. From hardware manual, register name is PCH_PIC_INT_ID instead. Here name PCH_PIC_INT_ID is used, and PCH_PIC_INT_ID + 4 is used for PCH_PIC_INT_ID_HI. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-2-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/s390x: Remove the obsolete hpage_1m_allowed switchThomas Huth1-4/+0
The s390-ccw-virtio-3.0 machine was the last one that used the hpage_1m_allowed switch. Since we removed this machine type, we can now remove the switch and the related code, too. This allows us to get rid of the get_machine_class() hack and the big fat warning comment there. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250506062148.306084-8-thuth@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-12Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into stagingStefan Hajnoczi2-2/+2
trivial patches for 2025-05-09 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEZKoqtTHVaQM2a/75gqpKJDselHgFAmgeawQACgkQgqpKJDse # lHgRcg/+LmwJJvMViRD/OJFRqp60zBnPyuXFyJJQ3q7lBsE5Vr8xdZUkrGUrQ0p+ # ef6KRnqesaYFH6lEZIJIYXLPalHDIJg6NCHnOphXYoexYQ61e8Y07lmTJlCXK+T8 # rTf230ZC0Jzuy6BM5cmk7cMnNtVp8gPgK5SOK4u5OJSQTBMDb/XZZkLdnjj5ChGJ # aX4qZ9fDLOWJoteXA4QWx6F8K1ONvooS5IMYB6AFJI2xMASq8nVETPXIuSComBDY # 2+krw8hLu6PoPd9yWjlnsE8y4NvNWyRAc2CVm3SI30PEIchvDiQuVJpUD5Q3xZy5 # 2OLD9nv9PqezERbD2ZdSa08VlbEeoyrRinBtZJv7m9qkiU8B4TGDn7hx23MAu6Zx # POF+P1Bc4kixL46pDMll5ETcRr6k184anTvpPWhOynJZBZusc4rX3UHSrVJMsfTx # DPjToUwRw50prtHyuYWWyoxZ+i9BOHAgiT/zOor2tte3xT/mvc8my9m2+YgDHnqE # u8wTnH3zYqexOwLctC3aslSbR1sqqrCsKOA8ZXQ33Ac6kV1q2T4Om4stmRbewjMG # ROsNky2iiKbPsSJsmZHVuv0vy3sHRVWyyp8ClSP5S+gNysEVu/Oka3E0KQ/vg72y # lDA3kNKS2t7ZSPXoLFaSWI6aOnSpKZgNW09wSVDh/AjKV+LbC6c= # =EoxT # -----END PGP SIGNATURE----- # gpg: Signature made Fri 09 May 2025 16:52:20 EDT # gpg: using RSA key 64AA2AB531D56903366BFEF982AA4A243B1E9478 # gpg: Good signature from "Michael Tokarev <mjt@debian.org>" [unknown] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [unknown] # gpg: aka "Michael Tokarev <mjt@tls.msk.ru>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 9D8B E14E 3F2A 9DD7 9199 28F1 61AD 3D98 ECDF 2C8E # Subkey fingerprint: 64AA 2AB5 31D5 6903 366B FEF9 82AA 4A24 3B1E 9478 * tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: (21 commits) docs/devel/testing/functional: Fix typo docs: replace `-hda` with `-drive` & update `root=` kernel parameter qapi/machine-target.json: fix "in in" typo in comment hw/display/apple-gfx.m: fix "in in" typo in comment qapi/qom.json: fix "the the" typo in comment include/hw/xen/interface/io/blkif.h: fix "the the" typo in comment include/exec/cpu-common.h: fix "the the" typo in comment hw/xen/xen-hvm-common.c: fix "the the" typo in comment block.c: fix "the the" typo in comment linux-user/mmap.c: fix "of of" typo in comment hw/acpi/pcihp: Fix typo in function name hw/pci-host/gpex-acpi: Fix typo in comment hw/net/e1000: Remove stray empty comment in header qom/object: Fix typo in comment hw/core/machine: Fix indentation hw/i386/acpi-build: Fix typo in function name hw/acpi/ich9: Remove ICH9_DEBUG macro hw/i386/acpi-build: Update document reference hw/i386/acpi-build: Fix typo and grammar in comment hw/isa/ich9: Remove stray empty comment ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-09include/hw/xen/interface/io/blkif.h: fix "the the" typo in commentMichael Tokarev1-1/+1
Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2025-05-09hw/acpi/pcihp: Fix typo in function nameGustavo Romero1-1/+1
Fix typo in QEMU's ACPI PCI hotplug API function name that checks whether a given bus is hotplug-capable. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2025-05-09Merge tag 'pull-vfio-20250509' of https://github.com/legoater/qemu into stagingStefan Hajnoczi2-2/+97
vfio queue: * Preparatory changes for the introduction of CPR support * Automatic enablement of OpRegion for IGD device passthrough * Linux headers update * Preparatory changes for the introduction of vfio-user # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmgd/0kACgkQUaNDx8/7 # 7KHRmRAArw1PXMCmoVBBeLcZ8BZPGjBZHtsvRzwS1yhVnNQadlpDlq4wd9HrfDFK # BTr7//Ag2Q1dKgibesh0A8hSjorXHUGQCmdkcCuGGTFnEwC86q5jCH1lUxgI0cs5 # 3bVwc43zhXGoKqmo07g4f2UFbjDYHe89LgWz2c7TFFGz7Tda/LCOdhnmXlXcIwz+ # v1ocutXd7VbDWvUzN7uZbf0SIH3Zj3p96dwmpLDtdzdliDA0JidNvS27+Z5gtvWe # O+1NW9MDzNfd6zLXCxL3GLeT61WZCe1dRCHEPX4cBo+DhnrifsC25DtJwYlDFvi2 # NMFfGzdKcEVSpeDp7WeM6MJgCZsGHC7ytmAKOKgN2M2kFSj3SI3sTFNlE1rzUhe6 # yjjCa59HzNLIi7L7xYCrVtCLGC/VXOp9kh67Sjs7FY7v778QUEdiudFBdBki7Bwh # bpRhdFJgCLHuKc6XrM7hsMnsRyM28MywyfHDo3M/pRSFNKfeImW6zSMXnyncZztK # W8e8OIz2DBMfH8pIu8hPw9Gsm5VAAs4aVmVFNa0CLl0oBko0Ew2YXcA5pTK5gGqv # x24uc/BhbLcfFUtK0OnP4N/B4rcoADebPV2u4eWoUK3aF5u4+7BY235bFuoTj+sb # 55DPDyWm5cmkX58Tdq46tD39dbD1hlUYkcydPbANH51wYx/lPpc= # =OqYP # -----END PGP SIGNATURE----- # gpg: Signature made Fri 09 May 2025 09:12:41 EDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-vfio-20250509' of https://github.com/legoater/qemu: (28 commits) vfio/container: pass listener_begin/commit callbacks vfio: add vfio-pci-base class vfio: add read/write to device IO ops vector vfio: add region info cache vfio: add device IO ops vector vfio: implement unmap all for DMA unmap callbacks vfio: add unmap_all flag to DMA unmap callback vfio: add vfio_pci_config_space_read/write() vfio: add strread/writeerror() vfio: consistently handle return value for helpers vfio: add vfio_device_get_irq_info() helper vfio: add vfio_attach_device_by_iommu_type() vfio: add vfio_device_unprepare() vfio: add vfio_device_prepare() linux-headers: Update to Linux v6.15-rc3 linux-header: update-linux-header script changes vfio/igd: Remove generation limitation for IGD passthrough vfio/igd: Only emulate GGC register when x-igd-gms is set vfio/igd: Allow overriding GMS with 0xf0 to 0xfe on Gen9+ vfio/igd: Enable OpRegion by default ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-09Merge tag 'docs-dep-pull-request' of https://gitlab.com/berrange/qemu into ↵Stefan Hajnoczi1-20/+38
staging Enable automated removal of deprecated versioned machine types * Remove test relying on 4.1 machine type that is about to be disabled * Fix off-by-1 in deprecation/removal logic for versioned machine types to cope with dev/rc versions * Enable logic for disabling registration of versioned machine types which have exceeded the 6 year lifetime policy. * Add automated version information to documentation about which versioned machine types are deprecated and removed # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE2vOm/bJrYpEtDo4/vobrtBUQT98FAmgc2GwACgkQvobrtBUQ # T9+gpA/+K08Np6taoY3XNYPc6CPxEVXJziR/4JT8wzVHKlz5aNjfWW4LewluRpNg # E+fnUaBWfdwvi2utRG/O+QvVFR5cHATpCBhGzJlAyKymQ7d4jyEjOqgW/euahmrb # A1KuLMmSNOUG5DiDKXnYpJxnfG/Vq36F4JRXlD+wbTtHImZnwkTGpOcaGcbnNQpn # CGC0ih1u1JWVlEWNzgR3pgJNoF5qd++aW6p2Nhl9shRRXs+ocIibkPVI733WwJCM # F11aRuwEAnCxxsS7BU6iSpToTByUQBvWihBJrisg+NvjkTzOG8uu1TBDUCabAU7v # TfjC6prVZPlt1U7tXZLFrw9bk6ldkA7ZiYp5xqCYXSX1pL1USLzwzfjsCglKTAmn # FV0Hn4Dk+TpiQ3KGEZsuRJ/PeRpYQTPlJAjUoC7xNmP1kSGo9yrZtMfOFUwf0MFe # N91N8XyhKiKhxr+CnAoVRiDAvZOts6Se8ELE4mGVXZevP7qd19pMyTQ0V/n6vPHB # GT84bJIcwoBBLjyM2ySOZsMnYTgRuYs1SdrjUaGrwfUnyBE0Sk1j/gTy02s3PdIM # Xcbbt2q4uuCfPF/Iu6ExROMooie8P13J0K13+njYDP6DSr+eG1YESN+qsQefNJYG # Vcf8Nct2LW1KNxt0NV2HkbCnTQu34JT4aw4yyFVTLPDlOFl0++E= # =fKhx # -----END PGP SIGNATURE----- # gpg: Signature made Thu 08 May 2025 12:14:36 EDT # gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full] # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full] # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * tag 'docs-dep-pull-request' of https://gitlab.com/berrange/qemu: include/hw/boards: add warning about changing deprecation logic docs/about/removed-features: auto-generate a note for versioned machine types docs/about/deprecated: auto-generate a note for versioned machine types include/hw/boards: cope with dev/rc versions in deprecation checks Revert "include/hw: temporarily disable deletion of versioned machine types" tests/qtest/q35-test: Remove the obsolete test_without_smram_base test Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-09vfio/container: pass listener_begin/commit callbacksJohn Levon1-0/+2
The vfio-user container will later need to hook into these callbacks; set up vfio to use them, and optionally pass them through to the container. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: John Levon <john.levon@nutanix.com> Link: https://lore.kernel.org/qemu-devel/20250507152020.1254632-15-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-09vfio: add read/write to device IO ops vectorJohn Levon1-0/+18
Now we have the region info cache, add ->region_read/write device I/O operations instead of explicit pread()/pwrite() system calls. Signed-off-by: John Levon <john.levon@nutanix.com> Link: https://lore.kernel.org/qemu-devel/20250507152020.1254632-13-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-09vfio: add region info cacheJohn Levon1-0/+1
Instead of requesting region information on demand with VFIO_DEVICE_GET_REGION_INFO, maintain a cache: this will become necessary for performance for vfio-user, where this call becomes a message over the control socket, so is of higher overhead than the traditional path. We will also need it to generalize region accesses, as that means we can't use ->config_offset for configuration space accesses, but must look up the region offset (if relevant) each time. Originally-by: John Johnson <john.g.johnson@oracle.com> Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Signed-off-by: John Levon <john.levon@nutanix.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250507152020.1254632-12-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-09vfio: add device IO ops vectorJohn Levon1-0/+38
For vfio-user, device operations such as IRQ handling and region read/writes are implemented in userspace over the control socket, not ioctl() to the vfio kernel driver; add an ops vector to generalize this, and implement vfio_device_io_ops_ioctl for interacting with the kernel vfio driver. Originally-by: John Johnson <john.g.johnson@oracle.com> Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Signed-off-by: John Levon <john.levon@nutanix.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250507152020.1254632-11-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-09vfio: add unmap_all flag to DMA unmap callbackJohn Levon1-2/+13
We'll use this parameter shortly; this just adds the plumbing. Signed-off-by: John Levon <john.levon@nutanix.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250507152020.1254632-9-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-09vfio: add strread/writeerror()John Levon1-0/+14
Add simple helpers to correctly report failures from read/write routines using the return -errno style. Signed-off-by: John Levon <john.levon@nutanix.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250507152020.1254632-7-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>