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2025-06-19hw/intc/loongarch_extioi: Add kernel irqchip save and restore functionBibo Mao1-0/+2
Add save and store funtction if kvm_irqchip_in_kernel() return true, it is to get and set ExtIOI irqchip state from KVM kernel. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-19hw/intc/loongarch_extioi: Add kernel irqchip realize functionBibo Mao1-0/+3
Function kvm_extioi_realize() is added if kvm_irqchip_in_kernel is set. It is to create and initialize ExtIOI device in kernel mode. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-2-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-16hw/intc/arm_gic: introduce a first-cpu-index propertyFrederic Konrad2-0/+5
This introduces a first-cpu-index property to the arm-gic, as some SOCs could have two separate GIC (ie: the zynqmp). Signed-off-by: Clément Chigot <chigot@adacore.com> Message-id: 20250526085523.809003-3-chigot@adacore.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: slightly expanded comment documenting GIC property] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-06-13hw/arm: make cpu targeted by arm_load_kernel the primary CPU.Clément Chigot1-0/+3
Currently, arm booting processus assumes that the first_cpu is the CPU that will boot: `arm_load_kernel` is powering off all but the `first_cpu`; `do_cpu_reset` is setting the loader address only for this `first_cpu`. For most of the boards, this isn't an issue as the kernel is loaded and booted on the first CPU anyway. However, for zynqmp, the option "boot-cpu" allows to choose any CPUs. Create a new arm_boot_info entry `primary_cpu` recording which CPU will be boot first. This one is set when `arm_boot_kernel` is called. Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250526085523.809003-2-chigot@adacore.com Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-06-11Merge tag 'pull-vfio-20250611' of https://github.com/legoater/qemu into stagingStefan Hajnoczi8-10/+136
vfio queue: * Fixed newly added potential issues in vfio-pci * Added support to report vfio-ap configuration changes * Added prerequisite support for vfio-user * Added first part for VFIO live update support # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmhJm00ACgkQUaNDx8/7 # 7KHBehAAlbSt+QCPwdNJ/5QPGGPWIQ86acIHaI/sE/lpcJx9FideQhtKTtt0gTOE # ZNGbzfeCnewCM+VLMgkrYZC9DWd9OpEO68tDy6ev577F6ijSR8wzXRtDl2j5Revm # R9gBuOm/cQ6Mafiv8SNPNSGW2tQ0M9Bd4GJRa5K3VBf8kFwPpWEZC/yDWbvSVvwc # 99TFXziIbWJEYGRzG4h7hoEEd/GapZOwTRIPRoRGHznbOPMsxShjIhExn8ZGTlU9 # woaNBPZXS5xjjy5tKyURexu+eyxbR6WsZFyeAA03+HzWEfRzhFc/rhAC6mBbpq7v # 03a/4ewkKZ0fYUf9G2H5YpXTXl6io+qk+irKi99/4GT0oSBMrm+/NcY7u9Hv2MwA # 50h3iXUhLQYzL2G2bSSoBTKOGxV84Xtto9j7dM7fy8e0nYv9rucvKl+V3Ox1Qwv4 # 8+bQsxP5tjmHlXE/n6ckfcrWtSHuWmb3JJ8yxdBttdo3Cz/+KxJ3UjtP9U81RXxY # gepxCRXZmcTfnv1dV6FyjOE6QOhB3WIT5rHmgoQIvHGhtBsLpT2mDlSsMVEQIXvm # ixQnRguwQv9fgEZeYB/ck/ezluOxewBlOv5Q3CPpHQBd2Ykh4N/8xsWpXlKI1KWr # Tj7Nh/2ObqNXbKdmb9nNiuo6eQDkPOm4mr1cs2ncMr7/cRGeKeA= # =KOf3 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 Jun 2025 11:05:49 EDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-vfio-20250611' of https://github.com/legoater/qemu: (27 commits) vfio: improve VFIODeviceIOOps docs vfio/pci: export MSI functions vfio/pci: vfio_notifier_cleanup vfio/pci: vfio_notifier_init cpr parameters vfio/pci: pass vector to virq functions vfio/pci: vfio_notifier_init vfio/pci: vfio_pci_vector_init vfio-pci: skip reset during cpr pci: skip reset during cpr pci: export msix_is_pending vfio/container: recover from unmap-all-vaddr failure vfio/container: mdev cpr blocker vfio/container: restore DMA vaddr vfio/container: discard old DMA vaddr vfio/container: preserve descriptors vfio/container: register container for cpr migration: lower handler priority migration: cpr helpers vfio: mark posted writes in region write callbacks vfio: add per-region fd support ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-06-11Merge tag 'hw-misc-20250610' of https://github.com/philmd/qemu into stagingStefan Hajnoczi6-8/+12
Misc HW patches # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmhILpoACgkQ4+MsLN6t # wN4FxA//U3xm1ZJLQnlS+AQp31foxgptVTNej+ZGOfvhYaUSBtFgUhoiXMPJPN4v # pKWBAFgWigaeM9f01T7H55M+Pj0Az2QLZw+Z6Bklu9RjzisZSuIdMZkPWiJXHBFC # 6OMh6pIjyxuYwYltai8gFFP5ENuILETMpFHEfFQtMiAimXhvDKvcQ5Dmi08UcamQ # hOFdia1djmVYIwJCi+V6Mwl/jwql/L1JpBrLyVOFmxGW8p5ZOjJTLL6pC7288dTP # B8Nb9MhWZpbsHiU4GalTOEXQUuAEa/KX9ZhUqW6kLVhguiD5JoCeMhTur40sX+/J # kKl8dSOhHJ0axEII5PxO4XviN1LWC4DATKfXxHjzvwNbJRH4gdBgaf8zqCeuy0TM # 7pOLzyn6ARXoJZTftS9Ezm1MCdCT5eOQ3+YMrLId8M+KBatogJ8uFMRHa8j+khhB # M08FOufxQGQYZsnz9eb+Dexh+Z3/EiUrCJt1X5icJEQ4uwvoo6lwxVnaV1RWYjRX # EnQOvFr38rctDq3UIckBGzfuVmolEc3l/QgENsNb0AIsz0K2P11Xfg3SNnnPBST8 # duFsWD1/nR53wcKrRli0PMezcH/QuUkRqzBlOc2wllcVKJrp71+m2VDClCmH6bBF # gk03V84b96rWkxwrxFB05mOVmdJKxAFAnwRRfIfYp69r9RgHx4A= # =m3BF # -----END PGP SIGNATURE----- # gpg: Signature made Tue 10 Jun 2025 09:09:46 EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20250610' of https://github.com/philmd/qemu: (24 commits) hw/net/i82596: Factor configure function out hw/net/i82596: Update datasheet URL hw/misc/stm32_rcc: Fix stm32_rcc_write() arguments order hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class hw/gpio/aspeed: Fix definition of AspeedGPIOClass hw/virtio/virtio-pmem: Fix definition of VirtIOPMEMClass hw/virtio/virtio-mem: Fix definition of VirtIOMEMClass tests/unit/test-char: Avoid using g_alloca() backends/tpm: Avoid using g_alloca() hw/gpio/pca9552: Avoid using g_newa() hw/core/cpu: Move CacheType to general cpu.h accel/hvf: Fix TYPE_HVF_ACCEL instance size tests/functional: Add a test for the Arduino UNO machine MAINTAINERS: Update Akihiko Odaki's affiliation pc-bios: ensure installed ROMs don't have execute permissions hw/ppc/e500: Use SysBusDevice API to access TYPE_CCSR's internal resources hw/net/fsl_etsec: Set default MAC address hw/ppc/e500: Move clock and TB frequency to machine class hw/hyperv/balloon: Consolidate OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES hw/core/resetcontainer: Consolidate OBJECT_DECLARE_SIMPLE_TYPE ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-06-11vfio: improve VFIODeviceIOOps docsJohn Levon1-9/+43
Explicitly describe every parameter rather than summarizing. Signed-off-by: John Levon <john.levon@nutanix.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250611104753.1199796-1-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-11vfio-pci: skip reset during cprSteve Sistare1-0/+2
Do not reset a vfio-pci device during CPR, and do not complain if the kernel's PCI config space changes for non-emulated bits between the vmstate save and load, which can happen due to ongoing interrupt activity. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/1749569991-25171-12-git-send-email-steven.sistare@oracle.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-11pci: skip reset during cprSteve Sistare1-0/+2
Do not reset a vfio-pci device during CPR. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Link: https://lore.kernel.org/qemu-devel/1749576403-25355-1-git-send-email-steven.sistare@oracle.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-11pci: export msix_is_pendingSteve Sistare1-0/+1
Export msix_is_pending for use by cpr. No functional change. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Link: https://lore.kernel.org/qemu-devel/1749569991-25171-10-git-send-email-steven.sistare@oracle.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-11vfio/container: recover from unmap-all-vaddr failureSteve Sistare2-0/+13
If there are multiple containers and unmap-all fails for some container, we need to remap vaddr for the other containers for which unmap-all succeeded. Recover by walking all address ranges of all containers to restore the vaddr for each. Do so by invoking the vfio listener callback, and passing a new "remap" flag that tells it to restore a mapping without re-allocating new userland data structures. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/1749569991-25171-9-git-send-email-steven.sistare@oracle.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-11vfio/container: mdev cpr blockerSteve Sistare2-0/+5
During CPR, after VFIO_DMA_UNMAP_FLAG_VADDR, the vaddr is temporarily invalid, so mediated devices cannot be supported. Add a blocker for them. This restriction will not apply to iommufd containers when CPR is added for them in a future patch. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/1749569991-25171-8-git-send-email-steven.sistare@oracle.com [ clg: Fixed context change in VFIODevice ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-11vfio/container: restore DMA vaddrSteve Sistare1-0/+3
In new QEMU, do not register the memory listener at device creation time. Register it later, in the container post_load handler, after all vmstate that may affect regions and mapping boundaries has been loaded. The post_load registration will cause the listener to invoke its callback on each flat section, and the calls will match the mappings remembered by the kernel. The listener calls a special dma_map handler that passes the new VA of each section to the kernel using VFIO_DMA_MAP_FLAG_VADDR. Restore the normal handler at the end. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/1749569991-25171-7-git-send-email-steven.sistare@oracle.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-11vfio/container: preserve descriptorsSteve Sistare1-0/+6
At vfio creation time, save the value of vfio container, group, and device descriptors in CPR state. On qemu restart, vfio_realize() finds and uses the saved descriptors. During reuse, device and iommu state is already configured, so operations in vfio_realize that would modify the configuration, such as vfio ioctl's, are skipped. The result is that vfio_realize constructs qemu data structures that reflect the current state of the device. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Link: https://lore.kernel.org/qemu-devel/1749569991-25171-5-git-send-email-steven.sistare@oracle.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-11vfio/container: register container for cprSteve Sistare2-0/+17
Register a legacy container for cpr-transfer, replacing the generic CPR register call with a more specific legacy container register call. Add a blocker if the kernel does not support VFIO_UPDATE_VADDR or VFIO_UNMAP_ALL. This is mostly boiler plate. The fields to to saved and restored are added in subsequent patches. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/1749569991-25171-4-git-send-email-steven.sistare@oracle.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-11vfio: mark posted writes in region write callbacksJohn Levon2-2/+3
For vfio-user, the region write implementation needs to know if the write is posted; add the necessary plumbing to support this. Signed-off-by: John Levon <john.levon@nutanix.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250607001056.335310-5-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-11vfio: add per-region fd supportJohn Levon1-2/+5
For vfio-user, each region has its own fd rather than sharing vbasedev's. Add the necessary plumbing to support this, and use the correct fd in vfio_region_mmap(). Signed-off-by: John Levon <john.levon@nutanix.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250607001056.335310-4-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-11hw/vfio/ap: Storing event information for an AP configuration change eventRorie Reyes1-0/+39
These functions can be invoked by the function that handles interception of the CHSC SEI instruction for requests indicating the accessibility of one or more adjunct processors has changed. Signed-off-by: Rorie Reyes <rreyes@linux.ibm.com> Reviewed-by: Anthony Krowiak <akrowiak@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250609164418.17585-4-rreyes@linux.ibm.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-10hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]ClassZhenzhong Duan1-4/+2
RISCVIOMMUPciClass and RISCVIOMMUSysClass are defined with missed parent class, class_init on them may corrupt their parent class fields. It's lucky that parent_realize and parent_phases are not initialized or used until now, so just remove the definitions. They can be added back when really necessary. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250606092406.229833-6-zhenzhong.duan@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-06-10hw/gpio/aspeed: Fix definition of AspeedGPIOClassZhenzhong Duan1-1/+1
AspeedGPIOClass's parent is SysBusDeviceClass rather than SysBusDevice. This isn't catastrophic only because sizeof(SysBusDevice) > sizeof(SysBusDeviceClass). Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500") Closes: https://lists.gnu.org/archive/html/qemu-devel/2025-06/msg00586.html Suggested-by: David Hildenbrand <david@redhat.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Message-ID: <20250606092406.229833-4-zhenzhong.duan@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-06-10hw/virtio/virtio-pmem: Fix definition of VirtIOPMEMClassZhenzhong Duan1-1/+1
VirtIOPMEMClass's parent is VirtioDeviceClass rather than VirtIODevice. This isn't catastrophic only because sizeof(VirtIODevice) > sizeof(VirtioDeviceClass). Fixes: 5f503cd9f388 ("virtio-pmem: add virtio device") Closes: https://lists.gnu.org/archive/html/qemu-devel/2025-06/msg00586.html Reported-by: David Hildenbrand <david@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Message-ID: <20250606092406.229833-3-zhenzhong.duan@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-06-10hw/virtio/virtio-mem: Fix definition of VirtIOMEMClassZhenzhong Duan1-1/+1
Parent of VirtIOMEMClass is VirtioDeviceClass rather than VirtIODevice. This isn't catastrophic only because sizeof(VirtIODevice) > sizeof(VirtioDeviceClass). Fixes: 910b25766b33 ("virtio-mem: Paravirtualized memory hot(un)plug") Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250606092406.229833-2-zhenzhong.duan@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-06-10hw/core/cpu: Move CacheType to general cpu.hZhao Liu1-0/+6
I386 has already defined cache types in target/i386/cpu.h. Move CacheType to hw/core/cpu.h, so that ARM and other architectures could use it. Cc: Alireza Sanaee <alireza.sanaee@huawei.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250605132722.3597593-1-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-06-10hw/core/resetcontainer: Consolidate OBJECT_DECLARE_SIMPLE_TYPEZhao Liu1-1/+1
The QOM type of ResettableContainer is defined by OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES, which means it doesn't need the class! Therefore, use OBJECT_DECLARE_SIMPLE_TYPE to declare the type, then there's no need for class definition. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250514084957.2221975-8-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-06-10hw/loongarch/virt: Remove global variables about memmap tablesBibo Mao2-3/+2
Global variables memmap_table and memmap_entries stores UEFI memory map table informations. It can be moved into structure LoongArchVirtMachineState. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250430094738.1556670-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-10hw/loongarch/virt: Remove global variables about initrdBibo Mao1-0/+2
Global variables initrd_offset and initrd_size records loading information about initrd, it can be moved to structure loongarch_boot_info. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250430094738.1556670-2-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-10hw/intc/loongarch_extioi: Fix typo issue about register EXTIOI_COREISR_ENDBibo Mao1-1/+1
Interrupt controller extioi supports 256 vectors, register EXTIOI_COREISR records pending interrupt status with bitmap method. Size of EXTIOI_COREISR is 256 / 8 = 0x20 bytes, EXTIOI_COREISR_END should be EXTIOI_COREISR_START + 0x20 rather than 0xB20. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250605092848.1550985-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-05vfio: move vfio-cpr.hSteve Sistare1-0/+18
Move vfio-cpr.h to include/hw/vfio, because it will need to be included by other files there. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Link: https://lore.kernel.org/qemu-devel/1748546679-154091-9-git-send-email-steven.sistare@oracle.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-05vfio: vfio_find_ram_discard_listenerSteve Sistare1-0/+3
Define vfio_find_ram_discard_listener as a subroutine so additional calls to it may be added in a subsequent patch. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Link: https://lore.kernel.org/qemu-devel/1748546679-154091-8-git-send-email-steven.sistare@oracle.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-05vfio/container: pass MemoryRegion to DMA operationsJohn Levon1-4/+5
Pass through the MemoryRegion to DMA operation handlers of vfio containers. The vfio-user container will need this later, to translate the vaddr into an offset for the dma map vfio-user message; CPR will also will need this. Originally-by: John Johnson <john.g.johnson@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Signed-off-by: John Levon <john.levon@nutanix.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Steve Sistare <steven.sistare@oracle.com> Link: https://lore.kernel.org/qemu-devel/20250521215534.2688540-1-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-05vfio: add more VFIOIOMMUClass docsJohn Levon1-3/+72
Add some additional doc comments for these class methods. Signed-off-by: John Levon <john.levon@nutanix.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250520162530.2194548-1-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-02Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi5-2/+358
into staging virtio,pci,pc: features, fixes, tests vhost will now no longer set a call notifier if unused some work towards loongarch testing based on bios-tables-test some core pci work for SVM support in vtd vhost vdpa init has been optimized for response time to QMP A couple more fixes Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCgAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmg97ZUPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpRBsH/0Fx4NNMaynXmVOgV1rMFirTydhQG5NSdeJv # i1RHd25Rne/RXH0CL71UPuOPADWh6bv9iZTg6RU6g7TwI8K9v3M0R71RlPLh1Lh1 # x7fifWNSNXVi18fM9/j+mIg7I2Ye0AaqveezRJWGzqoOxQKKlVI2xspKZBCCkygd # i2tgtR1ORB6+ji6wVoTDPlL42X5Jef5MUT3XOcRR5biHm0JfqxxQKVM83mD+5yMI # 0YqjT2BVRzo5rGN7mSuf7tQ50xI6I0wI1+eoWeKHRbg08f709M8TZRDKuVh24Evg # 9WnIhKLTzRVdCNLNbw9h9EhxoANpWCyvmnn6GCfkJui40necFHY= # =0lO6 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 02 Jun 2025 14:29:41 EDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (26 commits) hw/i386/pc_piix: Fix RTC ISA IRQ wiring of isapc machine vdpa: move memory listener register to vhost_vdpa_init vdpa: move iova_tree allocation to net_vhost_vdpa_init vdpa: reorder listener assignment vdpa: add listener_registered vdpa: set backend capabilities at vhost_vdpa_init vdpa: reorder vhost_vdpa_set_backend_cap vdpa: check for iova tree initialized at net_client_start vhost: Don't set vring call if guest notifier is unused tests/qtest/bios-tables-test: Use MiB macro rather hardcode value tests/data/uefi-boot-images: Add ISO image for LoongArch system uefi-test-tools:: Add LoongArch64 support pci: Add a PCI-level API for PRI pci: Add a pci-level API for ATS pci: Add a pci-level initialization function for IOMMU notifiers memory: Store user data pointer in the IOMMU notifiers pci: Add an API to get IOMMU's min page size and virtual address width pci: Cache the bus mastering status in the device pcie: Helper functions to check to check if PRI is enabled pcie: Add a helper to declare the PRI capability for a pcie device ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-06-02vdpa: move iova_tree allocation to net_vhost_vdpa_initEugenio Pérez1-1/+15
As we are moving to keep the mapping through all the vdpa device life instead of resetting it at VirtIO reset, we need to move all its dependencies to the initialization too. In particular devices with x-svq=on need a valid iova_tree from the beginning. Simplify the code also consolidating the two creation points: the first data vq in case of SVQ active and CVQ start in case only CVQ uses it. Tested-by: Lei Yang <leiyang@redhat.com> Reviewed-by: Si-Wei Liu <si-wei.liu@oracle.com> Acked-by: Jason Wang <jasowang@redhat.com> Suggested-by: Si-Wei Liu <si-wei.liu@oracle.com> Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Signed-off-by: Jonah Palmer <jonah.palmer@oracle.com> Message-Id: <20250522145839.59974-7-jonah.palmer@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-06-02vdpa: add listener_registeredEugenio Pérez1-0/+6
Check if the listener has been registered or not, so it needs to be registered again at start. Tested-by: Lei Yang <leiyang@redhat.com> Reviewed-by: Si-Wei Liu <si-wei.liu@oracle.com> Acked-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Signed-off-by: Jonah Palmer <jonah.palmer@oracle.com> Message-Id: <20250522145839.59974-5-jonah.palmer@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-06-02vhost: Don't set vring call if guest notifier is unusedHuaitong Han1-0/+1
The vring call fd is set even when the guest does not use MSI-X (e.g., in the case of virtio PMD), leading to unnecessary CPU overhead for processing interrupts. The commit 96a3d98d2c("vhost: don't set vring call if no vector") optimized the case where MSI-X is enabled but the queue vector is unset. However, there's an additional case where the guest uses INTx and the INTx_DISABLED bit in the PCI config is set, meaning that no interrupt notifier will actually be used. In such cases, the vring call fd should also be cleared to avoid redundant interrupt handling. Fixes: 96a3d98d2c("vhost: don't set vring call if no vector") Reported-by: Zhiyuan Yuan <yuanzhiyuan@chinatelecom.cn> Signed-off-by: Jidong Xia <xiajd@chinatelecom.cn> Signed-off-by: Huaitong Han <hanht2@chinatelecom.cn> Message-Id: <20250522100548.212740-1-hanht2@chinatelecom.cn> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-06-01pci: Add a PCI-level API for PRICLEMENT MATHIEU--DRIF1-0/+130
A device can send a PRI request to the IOMMU using pci_pri_request_page. The PRI response is sent back using the notifier managed with pci_pri_register_notifier and pci_pri_unregister_notifier. Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Co-authored-by: Ethan Milon <ethan.milon@eviden.com> Message-Id: <20250520071823.764266-12-clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-06-01pci: Add a pci-level API for ATSCLEMENT MATHIEU--DRIF1-0/+126
Devices implementing ATS can send translation requests using pci_ats_request_translation. The invalidation events are sent back to the device using the iommu notifier managed with pci_iommu_register_iotlb_notifier / pci_iommu_unregister_iotlb_notifier. Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Co-authored-by: Ethan Milon <ethan.milon@eviden.com> Message-Id: <20250520071823.764266-11-clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-06-01pci: Add a pci-level initialization function for IOMMU notifiersCLEMENT MATHIEU--DRIF1-0/+33
This is meant to be used by ATS-capable devices. Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250520071823.764266-10-clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-06-01pci: Add an API to get IOMMU's min page size and virtual address widthCLEMENT MATHIEU--DRIF1-0/+26
This kind of information is needed by devices implementing ATS in order to initialize their translation cache. Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250520071823.764266-8-clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-06-01pci: Cache the bus mastering status in the deviceCLEMENT MATHIEU--DRIF1-0/+1
The cached is_master value is necessary to know if a device is allowed to issue ATS/PRI requests or not as these operations do not go through the master_enable memory region. Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250520071823.764266-7-clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-06-01pcie: Helper functions to check to check if PRI is enabledCLEMENT MATHIEU--DRIF1-0/+1
pri_enabled can be used to check whether the capability is present and enabled on a PCIe device Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250520071823.764266-6-clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-06-01pcie: Add a helper to declare the PRI capability for a pcie deviceCLEMENT MATHIEU--DRIF2-1/+7
Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250520071823.764266-5-clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-06-01pcie: Helper function to check if ATS is enabledCLEMENT MATHIEU--DRIF1-0/+1
ats_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250520071823.764266-4-clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-06-01pcie: Helper functions to check if PASID is enabledCLEMENT MATHIEU--DRIF1-0/+2
pasid_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250520071823.764266-3-clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-06-01pcie: Add helper to declare PASID capability for a pcie deviceCLEMENT MATHIEU--DRIF2-1/+10
Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250520071823.764266-2-clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-05-30Merge tag 'pull-target-arm-20250530-2' of ↵Stefan Hajnoczi2-19/+4
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/arm: Add GMAC devices to NPCM8XX SoC * hw/arm: Add missing psci_conduit to NPCM8XX SoC boot info * docs/interop: convert text files to restructuredText * target/arm: Some minor refactorings * tests/functional: Add a test for the Stellaris arm machines * hw/block: Drop unused nand.c # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmg5qPYZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3tXUD/9tKWMUEYl23gd9IB5Ee3xK # dcgG4Fzv0Ae8HLTd1agyhrg5S2LiXmFi37IO65d8Wxf7Y2TBU+kj1m3aB/C3w9Bx # VdHGfNsHAMuYdYCOEm9OvmuSMYSxDRd43pNWdBxbc9/MgLM24rImJ05YHoZFVGrY # S5olcZOl3/ttFHtigO4AYAbxkHMAJ5gDyNJiuk88IPx9WGYdmmM4mzJ/m17/Re01 # hdOUi0DKQO7kl+646knSU0dicu8NeO5rBAyJzu3vFBnvYXznjd9XaxF+A0Opl54P # aBUZz27nDLvnGQrN8B5CjevjUysko+KL/L4NRqebeQKhSe4C8tKFIDocRTGyOEoR # SAI0UpZbcX/mXt52aksSwMNG8oRvHOqpJRnNaaCZQoMjK7SlFwi6WctDpwiGt/Hu # WaVlXaC77YRiKf1RAgH2CxV04ts342v+bndjfi4vy8D4zbTvwgqKxg+qk3N+JBMR # ZUI5Gz3OcGXbw5awJAYbJmyo6qxBysmdHpPY8I1eW0ohzRx1rZ3Vka4yIje5mgO+ # 5yFpSy4GDRqNYKgGwlXRaseB38qKL4bEz0+uGzXYqdG7ACBz0xhT5H10npXkX/au # LumtwW1sohsv3Xf9oBHQ1WQel7LDcWGVEZHZn6q67mazjvivLjREvA74dq1e8bqD # zovTStIpBYRChXTRK1ShUQ== # =Xts4 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 30 May 2025 08:47:50 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250530-2' of https://git.linaro.org/people/pmaydell/qemu-arm: hw/block: Drop unused nand.c tests/functional: Add a test for the Stellaris arm machines target/arm/hvf: Include missing 'cpu-qom.h' header target/arm/kvm: Include missing 'cpu-qom.h' header target/arm/qmp: Include missing 'cpu.h' header target/arm/cpu-features: Include missing 'cpu.h' header hw/arm/boot: Include missing 'system/memory.h' header target/arm/cpregs: Include missing 'target/arm/cpu.h' header target/arm: Only link with zlib when TCG is enabled target/arm/hvf_arm: Avoid using poisoned CONFIG_HVF definition target/arm/tcg-stubs: compile file once (system) docs/interop: convert text files to restructuredText hw/arm: Add missing psci_conduit to NPCM8XX SoC boot info tests/qtest: Migrate GMAC test from 7xx to 8xx hw/arm: Add GMAC devices to NPCM8XX SoC Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-30Merge tag 'pull-request-2025-05-30' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi6-40/+1
staging * Functional tests improvements * Endianness improvements/clean-ups for the Microblaze machines * Remove obsolete -2.4 and -2.5 i440fx and q35 machine types and related code # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmg5mlARHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbX1eRAAjvTK4noIfzc9QQI7EyUafgdp65m44wwx # vfjlLbhmEnWFF11Qhovc6o36N4zF4Pt30mbXZs0gQaDR5H9RT8wrg9kShirhZX3O # 4raPHCJFBviUCktSg90eFtvuQnfVK9cBMB8PMRQix+V5wRXcCx+cc6ebnQZ+UHp4 # L2d+qKRoHCPRO/dvQth4Be7a5pXqFQeu4gq7i/w9PCa7O+akSM3lc8dsJPuCiXgQ # R7dkwsrRQzmiEC6aDmauNpsRRs0yptQs+9b83V4moLX07hk/R/I59EDFQqALLim7 # jmSbLnulKSSCeatV54PE/K4QxT62iA2OuJ6wo/vzVBGpzLdKE4aq99OcNPDxwWi0 # wc6xVDNtMyr81Ex4pZ0WgVKt57tDBIp9RijB5wTAhRPqKgnHtRGVNqX9TrsFls5L # jIyKgfTxFKf9RA/a53p3uUXNmpLDVG63AhA9jWrAUtGOGJ0V+cDD2hTygXai8XTS # 66aiEdMiuPFV2fApaEftcySFrMoT7RG1JHlcMjsTOpRdZF/x+rehFQKOHcdBeJ6r # /zJ18MXbd5vEcglBz8joPwHu3mt2NLew+IvLPoAlwMfrniiNnUC+IY2Jzz3jYpBI # WbbaesVG7J8SzJ6SwNOVuiCbiAImOkrxEz/8Jm783sZvWSzLYmwI9bBp9KXVxGty # ed14fLi8g5U= # =8SJJ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 30 May 2025 07:45:20 EDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2025-05-30' of https://gitlab.com/thuth/qemu: (25 commits) tests/unit/test-util-sockets: fix mem-leak on error object hw/net/vmxnet3: Merge DeviceRealize in InstanceInit hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_DISABLE_PCIE definition hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS definition hw/scsi/vmw_pvscsi: Convert DeviceRealize -> InstanceInit hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_DISABLE_PCIE_BIT definition hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_OLD_PCI_CONFIGURATION definition hw/core/machine: Remove hw_compat_2_5[] array hw/nvram/fw_cfg: Remove legacy FW_CFG_ORDER_OVERRIDE hw/i386/x86: Remove X86MachineClass::save_tsc_khz field hw/i386/pc: Remove deprecated pc-q35-2.5 and pc-i440fx-2.5 machines hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_DISABLE_PCIE definition hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_MIGRATE_EXTRA definition hw/net/e1000: Remove unused E1000_FLAG_MAC flag hw/core/machine: Remove hw_compat_2_4[] array hw/i386/pc: Remove pc_compat_2_4[] array hw/i386/pc: Remove PCMachineClass::broken_reserved_end field hw/i386/pc: Remove deprecated pc-q35-2.4 and pc-i440fx-2.4 machines docs: Deprecate the qemu-system-microblazeel binary hw/microblaze: Remove the big-endian variants of ml605 and xlnx-zynqmp-pmu ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-30Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi1-0/+45
* target/i386/kvm: Intel TDX support * target/i386/emulate: more lflags cleanups * meson: remove need for explicit listing of dependencies in hw_common_arch and target_common_arch * rust: small fixes * hpet: Reorganize register decoding to be more similar to Rust code * target/i386: fixes for AMD models * target/i386: new EPYC-Turin CPU model # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmg4BxwUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroP67gf+PEP4EDQP0AJUfxXYVsczGf5snGjz # ro8jYmKG+huBZcrS6uPK5zHYxtOI9bHr4ipTHJyHd61lyzN6Ys9amPbs/CRE2Q4x # Ky4AojPhCuaL2wHcYNcu41L+hweVQ3myj97vP3hWvkatulXYeMqW3/4JZgr4WZ69 # A9LGLtLabobTz5yLc8x6oHLn/BZ2y7gjd2LzTz8bqxx7C/kamjoDrF2ZHbX9DLQW # BKWQ3edSO6rorSNHWGZsy9BE20AEkW2LgJdlV9eXglFEuEs6cdPKwGEZepade4bQ # Rdt2gHTlQdUDTFmAbz8pttPxFGMC9Zpmb3nnicKJpKQAmkT/x4k9ncjyAQ== # =XmkU # -----END PGP SIGNATURE----- # gpg: Signature made Thu 29 May 2025 03:05:00 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (77 commits) target/i386/tcg/helper-tcg: fix file references in comments target/i386: Add support for EPYC-Turin model target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits target/i386: Add couple of feature bits in CPUID_Fn80000021_EAX target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits rust: make declaration of dependent crates more consistent docs: Add TDX documentation i386/tdx: Validate phys_bits against host value i386/tdx: Make invtsc default on i386/tdx: Don't treat SYSCALL as unavailable i386/tdx: Fetch and validate CPUID of TD guest target/i386: Print CPUID subleaf info for unsupported feature i386: Remove unused parameter "uint32_t bit" in feature_word_description() i386/cgs: Introduce x86_confidential_guest_check_features() i386/tdx: Define supported KVM features for TDX i386/tdx: Add XFD to supported bit of TDX i386/tdx: Add supported CPUID bits relates to XFAM i386/tdx: Add supported CPUID bits related to TD Attributes ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-30hw/core/machine: Remove hw_compat_2_5[] arrayPhilippe Mathieu-Daudé1-3/+0
The hw_compat_2_5[] array was only used by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got removed. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-13-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-30hw/nvram/fw_cfg: Remove legacy FW_CFG_ORDER_OVERRIDEPhilippe Mathieu-Daudé3-14/+1
The MachineClass::legacy_fw_cfg_order boolean was only used by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got removed. Remove it along with: - FW_CFG_ORDER_OVERRIDE_* definitions - fw_cfg_set_order_override() - fw_cfg_reset_order_override() - fw_cfg_order[] - rom_set_order_override() - rom_reset_order_override() Simplify CLI and pc_vga_init() / pc_nic_init(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-12-philmd@linaro.org> [thuth: Fix error from check_patch.pl wrt to an empty "for" loop] Signed-off-by: Thomas Huth <thuth@redhat.com>
generated by cgit v1.1 at 2025-09-19 03:26:39 +0000