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2020-09-18qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost29-29/+29
2020-09-18sifive: Use DECLARE_*CHECKER* macrosEduardo Habkost6-11/+12
2020-09-18sifive: Move QOM typedefs and add missing includesEduardo Habkost6-12/+24
2020-09-18sifive_u: Rename memmap enum constantsEduardo Habkost1-17/+17
2020-09-18sifive_e: Rename memmap enum constantsEduardo Habkost1-19/+19
2020-09-17x86: move cpu hotplug from pc to x86Gerd Hoffmann1-0/+10
2020-09-17x86: move acpi_dev from pc/microvmGerd Hoffmann3-2/+1
2020-09-17x86: constify x86_machine_is_*_enabledGerd Hoffmann1-2/+2
2020-09-17microvm/acpi: add minimal acpi supportGerd Hoffmann1-0/+9
2020-09-17microvm: make virtio irq base runtime configurableGerd Hoffmann1-1/+1
2020-09-17acpi: move acpi_dsdt_add_power_button() to gedGerd Hoffmann1-0/+1
2020-09-17acpi: ged: add x86 device variant.Gerd Hoffmann1-0/+4
2020-09-17acpi: ged: add control regsGerd Hoffmann1-0/+12
2020-09-15virtio-gpu: make virtio_gpu_ops staticGerd Hoffmann1-2/+1
2020-09-14hw/arm/npcm7xx: add board setup stub for CPU and UART clocksHavard Skinnemoen1-0/+1
2020-09-14hw/ssi: NPCM7xx Flash Interface Unit device modelHavard Skinnemoen2-0/+75
2020-09-14hw/mem: Stubbed out NPCM7xx Memory Controller modelHavard Skinnemoen2-0/+38
2020-09-14hw/nvram: NPCM7xx OTP device modelHavard Skinnemoen2-0/+82
2020-09-14hw/arm: Add two NPCM7xx-based machinesHavard Skinnemoen1-0/+19
2020-09-14hw/arm: Add NPCM730 and NPCM750 SoC modelsHavard Skinnemoen1-0/+85
2020-09-14hw/timer: Add NPCM7xx Timer device modelHavard Skinnemoen1-0/+78
2020-09-14hw/misc: Add NPCM7xx Clock Controller device modelHavard Skinnemoen1-0/+48
2020-09-14hw/misc: Add NPCM7xx System Global Control Registers device modelHavard Skinnemoen1-0/+43
2020-09-13Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell17-86/+319
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng1-0/+0
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng1-0/+0
2020-09-09hw/riscv: Move riscv_htif model to hw/charBin Meng1-0/+0
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng1-81/+0
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng1-0/+0
2020-09-09hw/riscv: Move sifive_gpio model to hw/gpioBin Meng3-2/+2
2020-09-09hw/riscv: Move sifive_u_otp model to hw/miscBin Meng2-1/+1
2020-09-09hw/riscv: Move sifive_u_prci model to hw/miscBin Meng2-1/+1
2020-09-09hw/riscv: Move sifive_e_prci model to hw/miscBin Meng1-0/+0
2020-09-09hw/riscv: sifive_u: Connect a DMA controllerBin Meng1-0/+11
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-1/+3
2020-09-09hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng1-0/+3
2020-09-09hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng1-0/+7
2020-09-09hw/net: cadence_gem: Add a new 'phy-addr' propertyBin Meng1-0/+2
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng1-0/+11
2020-09-09hw/dma: Add SiFive platform DMA controller emulationBin Meng1-0/+57
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng1-0/+4
2020-09-09hw/sd: Add Cadence SDHCI emulationBin Meng1-0/+47
2020-09-09hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng1-0/+20
2020-09-09hw/char: Add Microchip PolarFire SoC MMUART emulationBin Meng1-0/+61
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng1-0/+88
2020-09-09hw/riscv: hart: Add a new 'resetvec' propertyBin Meng1-0/+1
2020-09-09pc87312: Rename TYPE_PC87312_SUPERIO to TYPE_PC87312Eduardo Habkost1-2/+2
2020-09-09sabre: Rename SABRE_DEVICE to SABREEduardo Habkost1-1/+1
2020-09-09esp: Rename ESP_STATE to ESPEduardo Habkost1-1/+1
2020-09-09ahci: Rename ICH_AHCI to ICH9_AHCIEduardo Habkost1-1/+1
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