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AgeCommit message (Expand)AuthorFilesLines
2023-09-08riscv: spelling fixesMichael Tokarev1-1/+1
2023-07-10hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.Tommy Wu1-3/+6
2023-06-13hw/riscv/opentitan: Correct OpenTitanState parent type/sizePhilippe Mathieu-Daudé1-1/+2
2023-06-13hw/riscv/opentitan: Explicit machine type definitionPhilippe Mathieu-Daudé1-1/+2
2023-06-13hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definitionPhilippe Mathieu-Daudé1-0/+2
2023-03-06hw/riscv/virt: Enable basic ACPI infrastructureSunil V L1-0/+1
2023-03-06hw/riscv/virt: Add memmap pointer to RiscVVirtStateSunil V L1-0/+1
2023-03-06hw/riscv/virt: Add a switch to disable ACPISunil V L1-0/+2
2023-03-06hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fieldsSunil V L1-0/+2
2023-03-01hw/riscv: Move the dtb load bits outside of create_fdt()Bin Meng1-0/+1
2023-02-16hw/riscv/boot.c: make riscv_load_initrd() staticDaniel Henrique Barboza1-1/+0
2023-02-16hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza1-0/+1
2023-02-16hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza1-0/+1
2023-02-07hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza1-1/+1
2023-02-07hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza1-1/+3
2023-02-07include/hw/riscv/opentitan: update opentitan IRQsWilfred Mallawa1-7/+7
2023-01-20hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()Daniel Henrique Barboza1-2/+2
2023-01-20hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()Daniel Henrique Barboza1-3/+3
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza1-1/+1
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza1-2/+1
2023-01-20hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza1-2/+2
2023-01-20hw/riscv/sifive_u: use 'fdt' from MachineStateDaniel Henrique Barboza1-3/+0
2023-01-20hw/riscv/spike: use 'fdt' from MachineStateDaniel Henrique Barboza1-2/+0
2023-01-20hw/riscv/boot.c: Introduce riscv_find_firmware()Bin Meng1-0/+2
2023-01-20hw/riscv/boot.c: introduce riscv_default_firmware_name()Daniel Henrique Barboza1-0/+1
2023-01-20hw/riscv/boot.c: make riscv_find_firmware() staticDaniel Henrique Barboza1-1/+0
2023-01-08include: Include headers where neededMarkus Armbruster6-2/+10
2023-01-06hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0Bin Meng5-5/+5
2023-01-06hw/riscv: virt: Fix the value of "riscv, ndev" in the dtbBin Meng1-3/+2
2023-01-06hw/riscv: sifive_e: Fix the number of interrupt sources of PLICBin Meng1-1/+6
2023-01-06hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLICBin Meng1-1/+1
2023-01-06hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley1-0/+1
2023-01-06hw/riscv: pfsoc: add missing FICs as unimplementedConor Dooley1-0/+2
2023-01-06hw/riscv: virt: Remove the redundant ipi-id propertyAtish Patra1-1/+0
2023-01-06hw/riscv/opentitan: add aon_timer base unimplWilfred Mallawa1-0/+1
2023-01-06hw/riscv/opentitan: bump opentitanWilfred Mallawa1-5/+4
2022-10-14hw/riscv: virt: Enable booting S-mode firmware from pflashSunil V L1-0/+1
2022-09-27hw/riscv/sifive_e: Fix inheritance of SiFiveEStateBernhard Beschow1-1/+2
2022-09-27hw/riscv: opentitan: Expose the resetvec as a SoC propertyAlistair Francis1-0/+2
2022-09-07hw/riscv: virt: fix the plic's address cellsConor Dooley1-0/+1
2022-09-07hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripheralsConor Dooley1-1/+13
2022-09-07hw/riscv: opentitan: bump opentitan versionWilfred Mallawa1-5/+6
2022-09-07hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza1-1/+1
2022-05-11Clean up header guards that don't match their file nameMarkus Armbruster2-4/+5
2022-04-29hw/riscv: virt: Create a platform busAlistair Francis1-1/+6
2022-04-29hw/riscv: virt: Add a machine done notifierAlistair Francis1-0/+1
2022-04-22hw/riscv: boot: Support 64bit fdt address.Dylan Jhong1-2/+2
2022-04-22riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa1-9/+21
2022-03-03hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa1-1/+3
2022-03-03hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel1-1/+1
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