riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-08-16	Clean up inclusion of sysemu/sysemu.h	Markus Armbruster	1	-1/+0
2019-08-16	Include hw/hw.h exactly where needed	Markus Armbruster	1	-1/+0
2019-08-16	include: Make headers more self-contained	Markus Armbruster	11	-1/+23
2019-07-18	hw/riscv: Load OpenSBI as the default firmware	Alistair Francis	1	-0/+3
2019-06-27	hw/riscv: Add support for loading a firmware	Alistair Francis	1	-0/+2
2019-06-27	hw/riscv: Split out the boot functions	Alistair Francis	1	-0/+27
2019-06-23	RISC-V: Fix a memory leak when realizing a sifive_e	Palmer Dabbelt	1	-0/+2
2019-06-23	sifive_prci: Read and write PRCI registers	Nathaniel Graff	1	-0/+32
2019-05-24	target/riscv: Add a base 32 and 64 bit CPU	Alistair Francis	1	-2/+2
2019-05-24	SiFive RISC-V GPIO Device	Fabien Chouteau	2	-2/+78
2019-05-13	Clean up decorations and whitespace around header guards	Markus Armbruster	1	-1/+0
2019-04-04	riscv: plic: Fix incorrect irq calculation	Alistair Francis	3	-4/+4
2018-12-20	sifive_uart: Implement interrupt pending register	Nathaniel Graff	1	-0/+3
2018-12-20	sifive_u: Add clock DT node for GEM ethernet	Anup Patel	1	-1/+2
2018-12-20	hw/riscv/virt: Connect the gpex PCIe	Alistair Francis	1	-1/+12
2018-12-20	hw/riscv/virt: Increase the number of interrupts	Alistair Francis	1	-1/+1
2018-09-04	RISC-V: Use atomic_cmpxchg to update PLIC bitmaps	Michael Clark	1	-1/+0
2018-07-05	hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device	Alistair Francis	1	-2/+7
2018-07-05	hw/riscv/sifive_plic: Use gpios instead of irqs	Alistair Francis	1	-1/+0
2018-07-05	hw/riscv/sifive_e: Create a SiFive E SoC object	Alistair Francis	1	-2/+14
2018-07-05	hw/riscv/sifive_u: Create a SiFive U SoC object	Alistair Francis	1	-2/+14
2018-05-06	RISC-V: Make virt header comment title consistent	Michael Clark	1	-1/+1
2018-05-06	RISC-V: Make some header guards more specific	Michael Clark	2	-4/+4
2018-05-06	RISC-V: Remove unused class definitions	Michael Clark	4	-22/+0
2018-05-06	RISC-V: Use ROM base address and size from memmap	Michael Clark	1	-2/+0
2018-05-06	RISC-V: Replace hardcoded constants with enum values	Michael Clark	4	-0/+16
2018-03-07	SiFive Freedom U Series RISC-V Machine	Michael Clark	1	-0/+69
2018-03-07	SiFive Freedom E Series RISC-V Machine	Michael Clark	1	-0/+79
2018-03-07	SiFive RISC-V PRCI Block	Michael Clark	1	-0/+37
2018-03-07	SiFive RISC-V UART Device	Michael Clark	1	-0/+71
2018-03-07	RISC-V VirtIO Machine	Michael Clark	1	-0/+74
2018-03-07	SiFive RISC-V Test Finisher	Michael Clark	1	-0/+42
2018-03-07	RISC-V Spike Machines	Michael Clark	1	-0/+53
2018-03-07	SiFive RISC-V PLIC Block	Michael Clark	1	-0/+85
2018-03-07	SiFive RISC-V CLINT Block	Michael Clark	1	-0/+50
2018-03-07	RISC-V HART Array	Michael Clark	1	-0/+39
2018-03-07	RISC-V HTIF Console	Michael Clark	1	-0/+61