| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-03-03 | hw: riscv: opentitan: fixup SPI addresses | Wilfred Mallawa | 1 | -1/+3 |
| 2022-03-03 | hw/riscv: virt: Increase maximum number of allowed CPUs | Anup Patel | 1 | -1/+1 |
| 2022-03-03 | hw/riscv: virt: Add optional AIA IMSIC support to virt machine | Anup Patel | 1 | -3/+14 |
| 2022-03-03 | hw/riscv: virt: Add optional AIA APLIC support to virt machine | Anup Patel | 1 | -6/+20 |
| 2022-01-21 | hw/riscv: Remove macros for ELF BIOS image names | Anup Patel | 1 | -2/+0 |
| 2022-01-21 | hw/riscv: spike: Allow using binary firmware as bios | Anup Patel | 1 | -0/+1 |
| 2022-01-21 | target/riscv: Support start kernel directly by KVM | Yifei Jiang | 1 | -0/+1 |
| 2022-01-08 | hw/riscv: virt: Allow support for 32 cores | Alistair Francis | 1 | -1/+1 |
| 2021-10-28 | hw/riscv: microchip_pfsoc: Use the PLIC config helper function | Alistair Francis | 1 | -1/+0 |
| 2021-10-28 | hw/riscv: sifive_u: Use the PLIC config helper function | Alistair Francis | 1 | -1/+0 |
| 2021-10-28 | hw/riscv: boot: Add a PLIC config string function | Alistair Francis | 1 | -0/+2 |
| 2021-10-28 | hw/riscv: virt: Don't use a macro for the PLIC configuration | Alistair Francis | 1 | -1/+0 |
| 2021-10-22 | hw/riscv: opentitan: Update to the latest build | Alistair Francis | 1 | -3/+3 |
| 2021-09-21 | hw/riscv: virt: Add optional ACLINT support to virt machine | Anup Patel | 1 | -0/+2 |
| 2021-09-21 | sifive_u: Connect the SiFive PWM device | Alistair Francis | 1 | -1/+13 |
| 2021-07-15 | hw/riscv: opentitan: Add the flash alias | Alistair Francis | 1 | -0/+2 |
| 2021-07-15 | hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri | Alistair Francis | 1 | -0/+1 |
| 2021-06-24 | hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer | Alistair Francis | 1 | -1/+4 |
| 2021-06-08 | hw/riscv: Use macros for BIOS image names | Bin Meng | 1 | -0/+5 |
| 2021-05-11 | hw/opentitan: Update the interrupt layout | Alistair Francis | 1 | -8/+8 |
| 2021-05-11 | hw/riscv: Connect Shakti UART to Shakti platform | Vijai Kumar K | 1 | -0/+2 |
| 2021-05-11 | riscv: Add initial support for Shakti C machine | Vijai Kumar K | 1 | -0/+73 |
| 2021-03-22 | hw/riscv: microchip_pfsoc: Map EMMC/SD mux register | Bin Meng | 1 | -0/+1 |
| 2021-03-22 | hw/riscv: Add fw_cfg support to virt | Asherah Connor | 1 | -0/+2 |
| 2021-03-10 | hw/riscv: migrate fdt field to generic MachineState | Alex Bennée | 1 | -1/+0 |
| 2021-03-04 | hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value | Bin Meng | 1 | -1/+1 |
| 2021-03-04 | hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card | Bin Meng | 1 | -0/+3 |
| 2021-03-04 | hw/riscv: sifive_u: Add QSPI0 controller and connect a flash | Bin Meng | 1 | -0/+4 |
| 2021-01-16 | riscv: Pass RISCVHartArrayState by pointer | Alistair Francis | 1 | -3/+3 |
| 2020-12-17 | riscv/opentitan: Update the OpenTitan memory layout | Alistair Francis | 1 | -6/+17 |
| 2020-12-17 | hw/riscv: Use the CPU to determine if 32-bit | Alistair Francis | 1 | -3/+5 |
| 2020-12-17 | hw/riscv: boot: Remove compile time XLEN checks | Alistair Francis | 1 | -3/+5 |
| 2020-12-17 | riscv: virt: Remove target macro conditionals | Alistair Francis | 1 | -6/+0 |
| 2020-12-17 | riscv: spike: Remove target macro conditionals | Alistair Francis | 1 | -6/+0 |
| 2020-12-17 | hw/riscv: microchip_pfsoc: add QSPI NOR flash | Vitaly Wool | 1 | -0/+3 |
| 2020-11-03 | hw/riscv: microchip_pfsoc: Hook the I2C1 controller | Bin Meng | 1 | -0/+1 |
| 2020-11-03 | hw/riscv: microchip_pfsoc: Correct DDR memory map | Bin Meng | 1 | -1/+4 |
| 2020-11-03 | hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 | Bin Meng | 1 | -0/+1 |
| 2020-11-03 | hw/riscv: microchip_pfsoc: Connect the SYSREG module | Bin Meng | 1 | -0/+2 |
| 2020-11-03 | hw/riscv: microchip_pfsoc: Connect the IOSCB module | Bin Meng | 1 | -1/+3 |
| 2020-11-03 | hw/riscv: microchip_pfsoc: Connect DDR memory controller modules | Bin Meng | 1 | -0/+5 |
| 2020-10-22 | hw/riscv: Load the kernel after the firmware | Alistair Francis | 1 | -0/+3 |
| 2020-10-22 | hw/riscv: Add a riscv_is_32_bit() function | Alistair Francis | 1 | -0/+2 |
| 2020-10-22 | hw/riscv: Return the end address of the loaded firmware | Alistair Francis | 1 | -4/+4 |
| 2020-10-22 | hw/riscv: sifive_u: Allow specifying the CPU | Alistair Francis | 1 | -0/+1 |
| 2020-09-18 | Use OBJECT_DECLARE_SIMPLE_TYPE when possible | Eduardo Habkost | 2 | -6/+2 |
| 2020-09-18 | sifive_u: Rename memmap enum constants | Eduardo Habkost | 1 | -17/+17 |
| 2020-09-18 | sifive_e: Rename memmap enum constants | Eduardo Habkost | 1 | -19/+19 |
| 2020-09-13 | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200... | Peter Maydell | 13 | -642/+149 |
| 2020-09-09 | hw/riscv: Move sifive_test model to hw/misc | Bin Meng | 1 | -45/+0 |
