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path: root/include/hw/riscv
AgeCommit message (Expand)AuthorFilesLines
2018-12-20sifive_uart: Implement interrupt pending registerNathaniel Graff1-0/+3
2018-12-20sifive_u: Add clock DT node for GEM ethernetAnup Patel1-1/+2
2018-12-20hw/riscv/virt: Connect the gpex PCIeAlistair Francis1-1/+12
2018-12-20hw/riscv/virt: Increase the number of interruptsAlistair Francis1-1/+1
2018-09-04RISC-V: Use atomic_cmpxchg to update PLIC bitmapsMichael Clark1-1/+0
2018-07-05hw/riscv/sifive_u: Connect the Cadence GEM Ethernet deviceAlistair Francis1-2/+7
2018-07-05hw/riscv/sifive_plic: Use gpios instead of irqsAlistair Francis1-1/+0
2018-07-05hw/riscv/sifive_e: Create a SiFive E SoC objectAlistair Francis1-2/+14
2018-07-05hw/riscv/sifive_u: Create a SiFive U SoC objectAlistair Francis1-2/+14
2018-05-06RISC-V: Make virt header comment title consistentMichael Clark1-1/+1
2018-05-06RISC-V: Make some header guards more specificMichael Clark2-4/+4
2018-05-06RISC-V: Remove unused class definitionsMichael Clark4-22/+0
2018-05-06RISC-V: Use ROM base address and size from memmapMichael Clark1-2/+0
2018-05-06RISC-V: Replace hardcoded constants with enum valuesMichael Clark4-0/+16
2018-03-07SiFive Freedom U Series RISC-V MachineMichael Clark1-0/+69
2018-03-07SiFive Freedom E Series RISC-V MachineMichael Clark1-0/+79
2018-03-07SiFive RISC-V PRCI BlockMichael Clark1-0/+37
2018-03-07SiFive RISC-V UART DeviceMichael Clark1-0/+71
2018-03-07RISC-V VirtIO MachineMichael Clark1-0/+74
2018-03-07SiFive RISC-V Test FinisherMichael Clark1-0/+42
2018-03-07RISC-V Spike MachinesMichael Clark1-0/+53
2018-03-07SiFive RISC-V PLIC BlockMichael Clark1-0/+85
2018-03-07SiFive RISC-V CLINT BlockMichael Clark1-0/+50
2018-03-07RISC-V HART ArrayMichael Clark1-0/+39
2018-03-07RISC-V HTIF ConsoleMichael Clark1-0/+61