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Author
Files
Lines
2018-12-20
sifive_uart: Implement interrupt pending register
Nathaniel Graff
1
-0
/
+3
2018-12-20
sifive_u: Add clock DT node for GEM ethernet
Anup Patel
1
-1
/
+2
2018-12-20
hw/riscv/virt: Connect the gpex PCIe
Alistair Francis
1
-1
/
+12
2018-12-20
hw/riscv/virt: Increase the number of interrupts
Alistair Francis
1
-1
/
+1
2018-09-04
RISC-V: Use atomic_cmpxchg to update PLIC bitmaps
Michael Clark
1
-1
/
+0
2018-07-05
hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device
Alistair Francis
1
-2
/
+7
2018-07-05
hw/riscv/sifive_plic: Use gpios instead of irqs
Alistair Francis
1
-1
/
+0
2018-07-05
hw/riscv/sifive_e: Create a SiFive E SoC object
Alistair Francis
1
-2
/
+14
2018-07-05
hw/riscv/sifive_u: Create a SiFive U SoC object
Alistair Francis
1
-2
/
+14
2018-05-06
RISC-V: Make virt header comment title consistent
Michael Clark
1
-1
/
+1
2018-05-06
RISC-V: Make some header guards more specific
Michael Clark
2
-4
/
+4
2018-05-06
RISC-V: Remove unused class definitions
Michael Clark
4
-22
/
+0
2018-05-06
RISC-V: Use ROM base address and size from memmap
Michael Clark
1
-2
/
+0
2018-05-06
RISC-V: Replace hardcoded constants with enum values
Michael Clark
4
-0
/
+16
2018-03-07
SiFive Freedom U Series RISC-V Machine
Michael Clark
1
-0
/
+69
2018-03-07
SiFive Freedom E Series RISC-V Machine
Michael Clark
1
-0
/
+79
2018-03-07
SiFive RISC-V PRCI Block
Michael Clark
1
-0
/
+37
2018-03-07
SiFive RISC-V UART Device
Michael Clark
1
-0
/
+71
2018-03-07
RISC-V VirtIO Machine
Michael Clark
1
-0
/
+74
2018-03-07
SiFive RISC-V Test Finisher
Michael Clark
1
-0
/
+42
2018-03-07
RISC-V Spike Machines
Michael Clark
1
-0
/
+53
2018-03-07
SiFive RISC-V PLIC Block
Michael Clark
1
-0
/
+85
2018-03-07
SiFive RISC-V CLINT Block
Michael Clark
1
-0
/
+50
2018-03-07
RISC-V HART Array
Michael Clark
1
-0
/
+39
2018-03-07
RISC-V HTIF Console
Michael Clark
1
-0
/
+61