aboutsummaryrefslogtreecommitdiff
path: root/include/hw/riscv
AgeCommit message (Expand)AuthorFilesLines
2022-05-11Clean up header guards that don't match their file nameMarkus Armbruster2-4/+5
2022-04-29hw/riscv: virt: Create a platform busAlistair Francis1-1/+6
2022-04-29hw/riscv: virt: Add a machine done notifierAlistair Francis1-0/+1
2022-04-22hw/riscv: boot: Support 64bit fdt address.Dylan Jhong1-2/+2
2022-04-22riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa1-9/+21
2022-03-03hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa1-1/+3
2022-03-03hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel1-1/+1
2022-03-03hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel1-3/+14
2022-03-03hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel1-6/+20
2022-01-21hw/riscv: Remove macros for ELF BIOS image namesAnup Patel1-2/+0
2022-01-21hw/riscv: spike: Allow using binary firmware as biosAnup Patel1-0/+1
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang1-0/+1
2022-01-08hw/riscv: virt: Allow support for 32 coresAlistair Francis1-1/+1
2021-10-28hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis1-1/+0
2021-10-28hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis1-1/+0
2021-10-28hw/riscv: boot: Add a PLIC config string functionAlistair Francis1-0/+2
2021-10-28hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis1-1/+0
2021-10-22hw/riscv: opentitan: Update to the latest buildAlistair Francis1-3/+3
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel1-0/+2
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis1-1/+13
2021-07-15hw/riscv: opentitan: Add the flash aliasAlistair Francis1-0/+2
2021-07-15hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis1-0/+1
2021-06-24hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis1-1/+4
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng1-0/+5
2021-05-11hw/opentitan: Update the interrupt layoutAlistair Francis1-8/+8
2021-05-11hw/riscv: Connect Shakti UART to Shakti platformVijai Kumar K1-0/+2
2021-05-11riscv: Add initial support for Shakti C machineVijai Kumar K1-0/+73
2021-03-22hw/riscv: microchip_pfsoc: Map EMMC/SD mux registerBin Meng1-0/+1
2021-03-22hw/riscv: Add fw_cfg support to virtAsherah Connor1-0/+2
2021-03-10hw/riscv: migrate fdt field to generic MachineStateAlex Bennée1-1/+0
2021-03-04hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal valueBin Meng1-1/+1
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng1-0/+3
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng1-0/+4
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis1-3/+3
2020-12-17riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis1-6/+17
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis1-3/+5
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis1-3/+5
2020-12-17riscv: virt: Remove target macro conditionalsAlistair Francis1-6/+0
2020-12-17riscv: spike: Remove target macro conditionalsAlistair Francis1-6/+0
2020-12-17hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool1-0/+3
2020-11-03hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng1-0/+1
2020-11-03hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng1-1/+4
2020-11-03hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng1-0/+1
2020-11-03hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng1-0/+2
2020-11-03hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng1-1/+3
2020-11-03hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng1-0/+5
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis1-0/+3
2020-10-22hw/riscv: Add a riscv_is_32_bit() functionAlistair Francis1-0/+2
2020-10-22hw/riscv: Return the end address of the loaded firmwareAlistair Francis1-4/+4
2020-10-22hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis1-0/+1
generated by cgit v1.1 at 2024-12-30 20:07:52 +0000