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path: root/include/hw/ppc/pnv_xscom.h
AgeCommit message (Expand)AuthorFilesLines
2024-07-26hw/ssi: Add SPI modelChalapathi V1-0/+3
2024-07-26ppc/pnv: Remove ppc target dependency from pnv_xscom.hChalapathi V1-1/+1
2024-07-26ppc/pnv: Begin a more complete ADU LPC model for POWER9/10Nicholas Piggin1-0/+6
2024-02-23ppc/pnv: Add POWER9/10 chiptod modelNicholas Piggin1-0/+9
2024-02-23hw/ppc: Add N1 chiplet modelChalapathi V1-0/+6
2024-02-23hw/ppc: Add pnv nest pervasive common chiplet modelChalapathi V1-0/+3
2023-11-07ppc/pnv: Connect PNV I2C controller to powernv10Glenn Miles1-0/+3
2023-11-07ppc/pnv: Add an I2C controller modelCédric Le Goater1-0/+3
2023-10-19hw/ppc/pnv_xscom: Move sysbus_mmio_map() call within pnv_xscom_init()Philippe Mathieu-Daudé1-1/+1
2023-10-19hw/ppc/pnv_xscom: Rename pnv_xscom_realize(Error **) -> pnv_xscom_init()Philippe Mathieu-Daudé1-1/+1
2023-07-07ppc/pnv: Add QME region for P10Joel Stanley1-0/+11
2023-07-07ppc/pnv: Set P10 core xscom region size to match hardwareNicholas Piggin1-1/+1
2023-07-07ppc/pnv: Add P10 quad xscom modelJoel Stanley1-1/+1
2023-01-20include/hw/ppc: Supply a few missing includesMarkus Armbruster1-1/+2
2022-08-31ppc/pnv: Add initial P9/10 SBE modelNicholas Piggin1-0/+12
2022-03-02ppc/pnv: Add a HOMER model to POWER10Cédric Le Goater1-0/+3
2022-03-02ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridgeCédric Le Goater1-0/+6
2022-03-02ppc/pnv: Add a OCC model for POWER10Cédric Le Goater1-0/+3
2022-03-02ppc/pnv: Add a XIVE2 controller to the POWER10 chipCédric Le Goater1-0/+3
2021-03-09exec/memory: Use struct Object typedefPhilippe Mathieu-Daudé1-1/+1
2020-11-15non-virt: Fix Lesser GPL version numberChetan Pant1-1/+1
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost1-4/+1
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost1-2/+3
2020-02-02ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridgeCédric Le Goater1-0/+9
2020-02-02ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridgeBenjamin Herrenschmidt1-0/+11
2019-12-17ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom()Greg Kurz1-1/+2
2019-12-17ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom()Greg Kurz1-1/+2
2019-12-17ppc: Drop useless extern annotation for functionsGreg Kurz1-11/+11
2019-12-17ppc/pnv: Introduce PBA registersCédric Le Goater1-0/+6
2019-12-17ppc/pnv: Make PnvXScomInterface an incomplete typeGreg Kurz1-4/+2
2019-12-17ppc/pnv: add a PSI bridge model for POWER10Cédric Le Goater1-0/+3
2019-12-17ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machineCédric Le Goater1-0/+19
2019-07-02ppc/pnv: fix XSCOM MMIO base address for P9 machines with multiple chipsCédric Le Goater1-1/+1
2019-05-13Clean up ill-advised or unusual header guardsMarkus Armbruster1-3/+4
2019-03-12ppc/pnv: POWER9 XSCOM quad supportCédric Le Goater1-4/+8
2019-03-12ppc/pnv: add a OCC model for POWER9Cédric Le Goater1-0/+3
2019-03-12ppc/pnv: add a PSI bridge model for POWER9Cédric Le Goater1-0/+3
2019-03-12ppc/pnv: add a XIVE interrupt controller model for POWER9Cédric Le Goater1-0/+3
2018-01-27ppc/pnv: fix PnvChip redefinition in <hw/ppc/pnv_xscom.h>Cédric Le Goater1-2/+0
2018-01-17ppc/pnv: fix XSCOM core addressing on POWER9Cédric Le Goater1-2/+11
2018-01-10ppc/pnv: change powernv_ prefix to pnv_ for overall naming consistencyCédric Le Goater1-2/+2
2017-09-27ppc/pnv: Improve macro parenthesizationEric Blake1-1/+1
2017-04-26ppc/pnv: Add OCC model stub with interrupt supportBenjamin Herrenschmidt1-0/+3
2017-04-26ppc/pnv: Add cut down PSI bridge model and hookup external interruptCédric Le Goater1-0/+3
2016-11-15ppc/pnv: add a 'xscom_core_base' field to PnvChipClassCédric Le Goater1-3/+2
2016-11-15ppc/pnv: fix compile breakage on old gccCédric Le Goater1-2/+0
2016-10-28ppc/pnv: add a LPC controllerBenjamin Herrenschmidt1-0/+3
2016-10-28ppc/pnv: add XSCOM handlers to PnvCoreCédric Le Goater1-0/+19
2016-10-28ppc/pnv: add XSCOM infrastructureCédric Le Goater1-0/+56
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