aboutsummaryrefslogtreecommitdiff
path: root/include/hw/ppc/pnv.h
AgeCommit message (Expand)AuthorFilesLines
2020-04-07ppc/pnv: Create BMC devices only when defaults are enabledCédric Le Goater1-0/+2
2020-02-02ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridgeCédric Le Goater1-0/+4
2020-02-02ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridgeBenjamin Herrenschmidt1-0/+7
2020-02-02ppc/pnv: Add support for "hostboot" modeCédric Le Goater1-0/+2
2020-01-08pnv/xive: Deduce the PnvXive pointer from XiveTCTX::xptrGreg Kurz1-2/+0
2020-01-08ppc/pnv: Add a "pnor" const link property to the BMC internal simulatorGreg Kurz1-1/+1
2020-01-08ppc/pnv: Add an "nr-threads" property to the base chip classGreg Kurz1-0/+1
2020-01-08ppc/pnv: Introduce a "xics" property under the POWER8 chipCédric Le Goater1-0/+2
2019-12-17ppc/pnv: Drop PnvChipClass::typeGreg Kurz1-9/+0
2019-12-17ppc/pnv: Introduce PnvChipClass::xscom_pcba() methodGreg Kurz1-0/+1
2019-12-17ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpersGreg Kurz1-10/+0
2019-12-17ppc/pnv: Introduce PnvChipClass::xscom_core_base() methodGreg Kurz1-0/+1
2019-12-17ppc/pnv: Introduce PnvChipClass::intc_print_info() methodGreg Kurz1-0/+1
2019-12-17ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpersGreg Kurz1-10/+0
2019-12-17ppc/pnv: Introduce PnvMachineClass::dt_power_mgt()Greg Kurz1-2/+6
2019-12-17ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compatGreg Kurz1-0/+13
2019-12-17ppc/pnv: Fix OCC common area region mappingCédric Le Goater1-0/+4
2019-12-17ppc/pnv: Introduce PBA registersCédric Le Goater1-10/+6
2019-12-17ppc/pnv: add a LPC Controller model for POWER10Cédric Le Goater1-0/+4
2019-12-17ppc/pnv: add a PSI bridge model for POWER10Cédric Le Goater1-0/+9
2019-12-17ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machineCédric Le Goater1-0/+33
2019-12-17ppc/pnv: Clarify how the TIMA is accessed on a multichip systemCédric Le Goater1-0/+3
2019-12-17ppc/pnv: Fix TIMA indirect accessCédric Le Goater1-0/+2
2019-12-17ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helperCédric Le Goater1-0/+5
2019-12-17ppc/pnv: Instantiate cores separatelyGreg Kurz1-1/+1
2019-12-17ppc/pnv: Create BMC devices at machine initCédric Le Goater1-1/+1
2019-12-17ppc/pnv: Add HIOMAP commandsCédric Le Goater1-0/+1
2019-12-17ppc/pnv: Add a PNOR modelCédric Le Goater1-0/+3
2019-11-18ppc: Add intc_destroy() handlers to SpaprInterruptController/PnvChipGreg Kurz1-0/+1
2019-10-24ppc: Reset the interrupt presenter from the CPU reset handlerCédric Le Goater1-0/+1
2019-10-04hw/ppc/pnv_homer: add PowerNV homer device modelBalamuruhan S1-0/+3
2019-10-04hw/ppc/pnv_xscom: retrieve homer/occ base address from PBA BARsBalamuruhan S1-0/+18
2019-07-02ppc/pnv: remove xscom_base field from PnvChipCédric Le Goater1-4/+1
2019-07-02ppc/pnv: fix XSCOM MMIO base address for P9 machines with multiple chipsCédric Le Goater1-0/+3
2019-05-13Clean up ill-advised or unusual header guardsMarkus Armbruster1-3/+4
2019-03-12ppc/pnv: POWER9 XSCOM quad supportCédric Le Goater1-0/+4
2019-03-12ppc/pnv: add a OCC model for POWER9Cédric Le Goater1-0/+1
2019-03-12ppc/pnv: add a LPC Controller model for POWER9Cédric Le Goater1-0/+4
2019-03-12ppc/pnv: add a 'dt_isa_nodename' to the chipCédric Le Goater1-0/+2
2019-03-12ppc/pnv: add a PSI bridge model for POWER9Cédric Le Goater1-0/+6
2019-03-12ppc/pnv: add a PSI bridge class modelCédric Le Goater1-1/+1
2019-03-12ppc/pnv: introduce a new pic_print_info() operation to the chip modelCédric Le Goater1-0/+1
2019-03-12ppc/pnv: introduce a new dt_populate() operation to the chip modelCédric Le Goater1-0/+1
2019-03-12ppc/pnv: add a XIVE interrupt controller model for POWER9Cédric Le Goater1-0/+21
2019-01-09spapr: modify the prototype of the cpu_intc_create() methodCédric Le Goater1-1/+1
2018-06-21ppc/pnv: introduce Pnv8Chip and Pnv9Chip modelsCédric Le Goater1-1/+23
2018-06-21ppc/pnv: introduce a new isa_create() operation to the chip modelCédric Le Goater1-0/+1
2018-06-21ppc/pnv: introduce a new intc_create() operation to the chip modelCédric Le Goater1-0/+1
2018-01-17ppc/pnv: fix XSCOM core addressing on POWER9Cédric Le Goater1-1/+0
2018-01-17ppc/pnv: introduce pnv*_is_power9() helpersCédric Le Goater1-0/+10
generated by cgit v1.1 at 2025-01-28 10:22:14 +0000