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AgeCommit message (Expand)AuthorFilesLines
2023-08-31hw/i2c: spelling fixesMichael Tokarev1-1/+1
2023-08-31bulk: Do not declare function prototypes using 'extern' keywordPhilippe Mathieu-Daudé1-1/+1
2023-08-31Add i.MX7 SRC device implementationJean-Christophe Dubois1-0/+66
2023-07-10hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.Tommy Wu1-0/+60
2023-06-19hw/arm/raspi: Import Linux raspi definitions as 'raspberrypi-fw-defs.h'Sergey Kambalin1-0/+163
2023-06-06hw: arm: allwinner-sramc: Add SRAM Controller support for R40qianfan Zhao1-0/+69
2023-06-06hw/arm/allwinner-r40: add SDRAM controller deviceqianfan Zhao1-0/+108
2023-06-06hw/arm/allwinner-r40: add Clock Control Unitqianfan Zhao1-0/+65
2023-05-02hw/arm/bcm2835_property: Implement "get command line" messageDaniel Bertalan1-0/+1
2023-04-20lasi: fix RTC migrationPaolo Bonzini1-2/+1
2023-03-08hw/mips/itu: Pass SAAR using QOM link propertyPhilippe Mathieu-Daudé1-3/+2
2023-03-08hw/mips: Declare all length properties as unsignedPhilippe Mathieu-Daudé2-3/+3
2023-02-08Don't include headers already included by qemu/osdep.hMarkus Armbruster1-2/+0
2023-02-06input/adb: Only include header where neededBALATON Zoltan4-2/+4
2023-01-12hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()Philippe Mathieu-Daudé5-13/+11
2023-01-12hw/misc: Allwinner A10 DRAM Controller EmulationStrahinja Jankovic1-0/+68
2023-01-12hw/misc: Allwinner-A10 Clock Controller Module EmulationStrahinja Jankovic1-0/+67
2023-01-08include: Include headers where neededMarkus Armbruster9-3/+16
2023-01-08include/hw/pci: Split pci_device.h off pci.hMarkus Armbruster1-1/+1
2023-01-06hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley2-0/+4
2023-01-06hw/misc: pfsoc: add fabric clocks to ioscbConor Dooley1-0/+1
2022-12-16hw/misc: Convert TYPE_MOS6522 subclasses to 3-phase resetPeter Maydell1-1/+1
2022-12-15hw/misc: Move some arm-related files from specific_ss into softmmu_ssThomas Huth1-1/+1
2022-10-31hw/ppc/mac.h: Rename to include/hw/nvram/mac_nvram.hBALATON Zoltan1-1/+1
2022-10-31hw/ppc/mac.h: Move macio specific parts out from shared headerBALATON Zoltan1-0/+21
2022-07-14aspeed: sbc: Allow per-machine settingsJoel Stanley1-0/+13
2022-06-30hw/misc/aspeed: Add PECI controllerPeter Delevoryas1-0/+29
2022-06-09acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AMLIgor Mammedov1-9/+0
2022-05-11Clean up decorations and whitespace around header guardsMarkus Armbruster3-3/+3
2022-05-11Clean up header guards that don't match their file nameMarkus Armbruster5-11/+11
2022-05-08lasi: move from hw/hppa to hw/miscMark Cave-Ayland1-0/+78
2022-05-03aspeed/hace: Support AST1030 HACESteven Lee1-0/+2
2022-05-02aspeed/hace: Support AST2600 HACESteven Lee1-0/+4
2022-05-02aspeed/hace: Support HMAC Key Buffer register.Steven Lee1-0/+1
2022-05-02aspeed/scu: Add AST1030 supportSteven Lee1-0/+25
2022-05-02hw: aspeed_scu: Introduce clkin_25Mhz attributeSteven Lee1-0/+1
2022-05-02hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation functionSteven Lee1-0/+19
2022-04-21hw/misc: Add PWRON STRAP bit fields in GCR moduleHao Wu1-0/+30
2022-04-21hw/misc: Add a model of the Xilinx Versal CRLEdgar E. Iglesias1-0/+235
2022-03-18hw/misc: Add a model of the Xilinx ZynqMP APU ControlEdgar E. Iglesias1-0/+93
2022-03-18hw/misc: Add a model of the Xilinx ZynqMP CRFEdgar E. Iglesias1-0/+211
2022-03-09macio/pmu.c: remove redundant codeMark Cave-Ayland1-2/+0
2022-03-09mos6522: implement edge-triggering for CA1/2 and CB1/2 control line IRQsMark Cave-Ayland1-0/+15
2022-03-09mos6522: record last_irq_levels in mos6522_set_irq()Mark Cave-Ayland1-0/+1
2022-03-09mos6522: add "info via" HMP command for debuggingMark Cave-Ayland1-0/+2
2022-03-09mos6522: add register names to register read/write trace eventsMark Cave-Ayland1-0/+2
2022-03-09mos6522: remove update_irq() and set_sr_int() methods from MOS6522DeviceClassMark Cave-Ayland1-2/+0
2022-03-09mos6522: switch over to use qdev gpios for IRQsMark Cave-Ayland2-5/+2
2022-03-09mac_via: use IFR bit flag constants for VIA2 IRQsMark Cave-Ayland1-10/+9
2022-03-09mac_via: use IFR bit flag constants for VIA1 IRQsMark Cave-Ayland1-10/+10
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