aboutsummaryrefslogtreecommitdiff
path: root/include/hw/arm
AgeCommit message (Expand)AuthorFilesLines
2017-02-07aspeed: add a watchdog controllerCédric Le Goater1-0/+2
2017-01-27char: rename CharDriverState ChardevMarc-André Lureau2-4/+4
2017-01-20hw/arm/virt: Add board property to enable EL2Peter Maydell1-0/+1
2017-01-20hw/arm/virt: Support using SMC for PSCIPeter Maydell1-1/+1
2017-01-20hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPUPeter Maydell1-0/+2
2017-01-09hw/arm/virt: remove VirtGuestInfoAndrew Jones1-5/+1
2017-01-09hw/arm/virt-acpi-build: remove redundant members from VirtGuestInfoAndrew Jones1-6/+0
2017-01-09hw/arm/virt: pass VirtMachineState instead of VirtGuestInfoAndrew Jones1-1/+1
2017-01-09hw/arm/virt: move VirtMachineState/Class to virt.hAndrew Jones1-0/+37
2017-01-09hw/arm/virt: remove include/hw/arm/virt-acpi-build.hAndrew Jones2-40/+13
2017-01-09hw/arm/virt: eliminate struct VirtGuestInfoStateAndrew Jones1-6/+0
2017-01-09hw/arm/virt-acpi-build: name GIC CPU Interface Structure appropriatelyAndrew Jones1-2/+0
2016-12-27aspeed: add a memory region for SRAMCédric Le Goater1-0/+2
2016-12-27aspeed: QOMify the CPU object and attach it to the SoCCédric Le Goater1-1/+1
2016-12-20Move target-* CPU file into a target/ folderThomas Huth4-4/+4
2016-10-17hw/arm/virt: no ITS on older machine typesAndrew Jones1-0/+1
2016-10-17aspeed: add support for the AST2500 SoC SMC controllersCédric Le Goater1-0/+2
2016-10-17aspeed: extend the number of host SPI controllersCédric Le Goater1-1/+5
2016-10-17aspeed: rename the smc object to fmcCédric Le Goater1-1/+1
2016-10-04STM32F205: Connect the SPI devicesAlistair Francis1-0/+3
2016-10-04STM32F205: Connect the ADC devicesAlistair Francis1-0/+6
2016-09-22aspeed-soc: provide a framework to add new SoCsCédric Le Goater1-1/+16
2016-09-22ast2400: replace ast2400 with aspeed_socCédric Le Goater1-8/+8
2016-09-22ast2400: rename the Aspeed SoC files to aspeed_socCédric Le Goater1-0/+0
2016-09-15Remove unused function declarationsLadi Prosek1-1/+0
2016-09-06ast2400: add a memory controller device modelCédric Le Goater1-0/+2
2016-07-12Clean up decorations and whitespace around header guardsMarkus Armbruster2-4/+4
2016-07-12Clean up ill-advised or unusual header guardsMarkus Armbruster1-4/+3
2016-07-12Clean up header guards that don't match their file nameMarkus Armbruster2-5/+5
2016-07-04ast2400: add SMC controllers (FMC and SPI)Cédric Le Goater1-0/+3
2016-06-27ast2400: Integrate the SCU model and set silicon revisionAndrew Jeffery1-0/+2
2016-06-14arm: xlnx-zynqmp: Add xlnx-dp and xlnx-dpdmaKONRAD Frederic1-0/+4
2016-06-14hw/arm/virt: Add PMU node for virt machineShannon Zhao1-0/+4
2016-06-06xlnx-zynqmp: Make the RPU subsystem optionalEdgar E. Iglesias1-0/+2
2016-06-06xlnx-zynqmp: Add a secure prop to en/disable ARM Security ExtensionsEdgar E. Iglesias1-0/+3
2016-06-06i2c: add aspeed i2c controllerCédric Le Goater1-0/+2
2016-06-02Add ENET device to i.MX6 SOC.Jean-Christophe Dubois1-2/+4
2016-05-19qemu-common: push cpu.h inclusion out of qemu-common.hPaolo Bonzini4-0/+4
2016-05-19arm: remove useless cpu.h inclusionPaolo Bonzini1-2/+0
2016-05-19arm: include cpu-qom.h in files that require ARMCPUPaolo Bonzini4-1/+4
2016-05-12i.MX: Add i.MX6 SOC implementation.Jean-Christophe DUBOIS1-0/+450
2016-03-16bcm2835_dma: add emulation of Raspberry Pi DMA controllerGrégory ESTRADE1-0/+2
2016-03-16bcm2835_fb: add framebuffer device for Raspberry PiGrégory ESTRADE1-0/+2
2016-03-16bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) blockAndrew Baumann1-0/+2
2016-03-16hw/arm: Add ASPEED AST2400 SoC modelAndrew Jeffery1-0/+35
2016-03-04arm: boot: Support big-endian elfsPeter Crosthwaite1-0/+9
2016-03-04hw/arm/virt: Provide a secure-only RAM if booting in Secure modePeter Maydell1-0/+1
2016-02-03arm/boot: move highbank secure board setup code to common routineAndrew Baumann1-0/+5
2016-02-03bcm2836: add bcm2836 SoC deviceAndrew Baumann1-0/+35
2016-02-03bcm2835_peripherals: add rollup device for bcm2835 peripheralsAndrew Baumann2-0/+170
generated by cgit v1.1 at 2025-02-11 18:10:35 +0000