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2019-08-16include: Make headers more self-containedMarkus Armbruster1-0/+2
Back in 2016, we discussed[1] rules for headers, and these were generally liked: 1. Have a carefully curated header that's included everywhere first. We got that already thanks to Peter: osdep.h. 2. Headers should normally include everything they need beyond osdep.h. If exceptions are needed for some reason, they must be documented in the header. If all that's needed from a header is typedefs, put those into qemu/typedefs.h instead of including the header. 3. Cyclic inclusion is forbidden. This patch gets include/ closer to obeying 2. It's actually extracted from my "[RFC] Baby steps towards saner headers" series[2], which demonstrates a possible path towards checking 2 automatically. It passes the RFC test there. [1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org> https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html [2] Message-Id: <20190711122827.18970-1-armbru@redhat.com> https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.html Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190812052359.30071-2-armbru@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-06-12Supply missing header guardsMarkus Armbruster1-0/+5
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190604181618.19980-5-armbru@redhat.com>
2019-02-26softfloat: Implement float128_to_uint32David Hildenbrand1-0/+1
Handling it just like float128_to_uint32_round_to_zero, that hopefully is free of bugs :) Documentation basically copied from float128_to_uint64 Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-02-26softfloat: add float128_is_{normal,denormal}David Hildenbrand1-2/+12
Needed on s390x, to test for the data class of a number. So it will gain soon a user. A number is considered normal if the exponent is neither 0 nor all 1's. That can be checked by adding 1 to the exponent, and comparing against >= 2 after dropping an eventual overflow into the sign bit. While at it, convert the other floatXX_is_normal functions to use a similar, less error prone calculation, as suggested by Richard H. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-01-22include/fpu/softfloat: Fix compilation with Clang on s390xThomas Huth1-1/+1
Clang v7.0.1 does not like the __int128 variable type for inline assembly on s390x: In file included from fpu/softfloat.c:97: include/fpu/softfloat-macros.h:647:9: error: inline asm error: This value type register class is not natively supported! asm("dlgr %0, %1" : "+r"(n) : "r"(d)); ^ Disable this code part there now when compiling with Clang, so that the generic code gets used instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-12-17softfloat: add float{32,64}_is_zero_or_normalEmilio G. Cota1-0/+10
These will gain some users very soon. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-12-17softfloat: add float{32,64}_is_{de,}normalEmilio G. Cota1-0/+20
This paves the way for upcoming work. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-11-04softfloat: Don't execute divdeu without power7Richard Henderson1-2/+2
The divdeu instruction was added to ISA 2.06 (Power7). Exclude this block from older cpus. Fixes: 27ae5109a2ba (softfloat: Specialize udiv_qrnnd for ppc64) Reported-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-05softfloat: Specialize udiv_qrnnd for ppc64Richard Henderson1-0/+16
The ISA has a 128/64-bit division instruction, though it assumes the low 64-bits of the numerator are 0, and so requires a bit more fixup than a full 128-bit division insn. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-05softfloat: Specialize udiv_qrnnd for s390xRichard Henderson1-0/+6
The ISA has a 128/64-bit division instruction. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-05softfloat: Specialize udiv_qrnnd for x86_64Richard Henderson1-0/+6
The ISA has a 128/64-bit division instruction. Tested-by: Emilio G. Cota <cota@braap.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-05softfloat: Fix divisionRichard Henderson1-9/+25
The __udiv_qrnnd primitive that we nicked from gmp requires its inputs to be normalized. We were not doing that. Because the inputs are nearly normalized already, finishing that is trivial. Replace div128to64 with a "proper" udiv_qrnnd, so that this remains a reusable primitive. Fixes: cf07323d494 Fixes: https://bugs.launchpad.net/qemu/+bug/1793119 Tested-by: Emilio G. Cota <cota@braap.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-05softfloat: Replace countLeadingZeros32/64 with clz32/64Thomas Huth1-87/+0
Our minimum required compiler for compiling QEMU is GCC 4.1 these days, so we can drop the support for compilers which do not provide the __builtin_clz*() functions yet. Since the countLeadingZeros32/64 are then identical to the clz32/64 functions, and we do not have to sync the softloat 2 codebase with upstream anymore (softloat 3 is a complete rewrite) we can simply replace the functions with our QEMU versions. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1538118095-7003-1-git-send-email-thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-05softfloat: remove float64_trunc_to_intEmilio G. Cota1-1/+0
It has not had users since f83311e476 ("target-m68k: use floatx80 internally", 2017-06-21). Note that no other bit-width has floatX_trunc_to_int. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-08-24softfloat: Add scaling float-to-int routinesRichard Henderson1-20/+59
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180814002653.12828-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-24softfloat: Add scaling int-to-float routinesRichard Henderson1-13/+39
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180814002653.12828-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-17fpu/softfloat: Specialize on snan_bit_is_oneRichard Henderson1-0/+1
Only MIPS requires snan_bit_is_one to be variable. While we are specializing softfloat behaviour, allow other targets to eliminate this runtime check. Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@mips.com> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Alexander Graf <agraf@suse.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17fpu/softfloat: Remove floatX_maybe_silence_nanRichard Henderson1-5/+0
These functions are now unused. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17fpu/softfloat: re-factor float to float conversionsAlex Bennée1-4/+4
This allows us to delete a lot of additional boilerplate code which is no longer needed. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17fpu/softfloat: Split floatXX_silence_nan from floatXX_maybe_silence_nanRichard Henderson1-0/+5
The new function assumes that the input is an SNaN and does not double-check. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-03-04softfloat: use floatx80_infinity in softfloatLaurent Vivier1-2/+11
Since f3218a8 ("softfloat: add floatx80 constants") floatx80_infinity is defined but never used. This patch updates floatx80 functions to use this definition. This allows to define a different default Infinity value on m68k: the m68k FPU defines infinity with all bits set to zero in the mantissa. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180224201802.911-4-laurent@vivier.eu>
2018-03-04softfloat: export some functionsLaurent Vivier2-0/+962
Move fpu/softfloat-macros.h to include/fpu/ Export floatx80 functions to be used by target floatx80 specific implementations. Exports: propagateFloatx80NaN(), extractFloatx80Frac(), extractFloatx80Exp(), extractFloatx80Sign(), normalizeFloatx80Subnormal(), packFloatx80(), roundAndPackFloatx80(), normalizeRoundAndPackFloatx80() Also exports packFloat32() that will be used to implement m68k fsinh, fcos, fsin, ftan operations. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180224201802.911-2-laurent@vivier.eu>
2018-03-01arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16Alex Bennée1-4/+12
As some of the constants here will also be needed elsewhere (specifically for the upcoming SVE support) we move them out to softfloat.h. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-13-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-21fpu/softfloat: re-factor sqrtAlex Bennée1-0/+1
This is a little bit of a departure from softfloat's original approach as we skip the estimate step in favour of a straight iteration. There is a minor optimisation to avoid calculating more bits of precision than we need however this still brings a performance drop, especially for float64 operations. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21fpu/softfloat: re-factor compareAlex Bennée1-0/+2
The compare function was already expanded from a macro. I keep the macro expansion but move most of the logic into a compare_decomposed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21fpu/softfloat: re-factor minmaxAlex Bennée1-0/+6
Let's do the same re-factor treatment for minmax functions. I still use the MACRO trick to expand but now all the checking code is common. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21fpu/softfloat: re-factor scalbnAlex Bennée1-0/+1
This is one of the simpler manipulations you could make to a floating point number. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21fpu/softfloat: re-factor int/uint to floatAlex Bennée1-21/+9
These are considerably simpler as the lower order integers can just use the higher order conversion function. As the decomposed fractional part is a full 64 bit rounding and inexact handling comes from the pack functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21fpu/softfloat: re-factor float to int/uintAlex Bennée1-0/+13
We share the common int64/uint64_pack_decomposed function across all the helpers and simply limit the final result depending on the final size. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21fpu/softfloat: re-factor round_to_intAlex Bennée1-0/+1
We can now add float16_round_to_int and use the common round_decomposed and canonicalize functions to have a single implementation for float16/32/64 round_to_int functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-21fpu/softfloat: re-factor muladdAlex Bennée1-0/+1
We can now add float16_muladd and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 muladd functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-21fpu/softfloat: re-factor divAlex Bennée1-0/+1
We can now add float16_div and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 versions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-21fpu/softfloat: re-factor mulAlex Bennée1-0/+1
We can now add float16_mul and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 versions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-21fpu/softfloat: re-factor add/subAlex Bennée1-0/+4
We can now add float16_add/sub and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 add and sub functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-02-21include/fpu/softfloat: add some float16 constantsAlex Bennée1-3/+5
This defines the same set of common constants for float 16 as defined for 32 and 64 bit floats. These are often used by target helper functions. I've also removed constants that are not used by anybody. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21include/fpu/softfloat: implement float16_set_sign helperAlex Bennée1-0/+5
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21include/fpu/softfloat: implement float16_chs helperAlex Bennée1-0/+9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-21include/fpu/softfloat: implement float16_abs helperAlex Bennée1-0/+7
This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée2-53/+64
As cpu.h is another typically widely included file which doesn't need full access to the softfloat API we can remove the includes from here as well. Where they do need types it's typically for float_status and the rounding modes so we move that to softfloat-types.h as well. As a result of not having softfloat in every cpu.h call we now need to add it to various helpers that do need the full softfloat.h definitions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [For PPC parts] Acked-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-21fpu/softfloat-types: new header to prevent excessive re-buildsAlex Bennée2-30/+116
The main culprit here is bswap.h which pulled in softfloat.h so it could use the types in its CPU_Float* and ldfl/stfql functions. As bswap.h is very widely included this added a compile dependency every time we touch softfloat.h. Move the typedefs for each float type into their own file so we don't re-build the world every time we tweak the main softfloat.h header. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21include/fpu/softfloat: remove USE_SOFTFLOAT_STRUCT_TYPESAlex Bennée1-27/+0
It's not actively built and when enabled things fail to compile. I'm not sure the type-checking is really helping here. Seeing as we "own" our softfloat now lets remove the cruft. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-21fpu/softfloat: implement float16_squash_input_denormalAlex Bennée1-0/+1
This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-21configure: Drop ancient Solaris 9 and earlier supportPeter Maydell1-5/+0
Solaris 9 was released in 2002, its successor Solaris 10 was released in 2005, and Solaris 9 was end-of-lifed in 2014. Nobody has stepped forward to express interest in supporting Solaris of any flavour, so removing support for the ancient versions seems uncontroversial. In particular, this allows us to remove a use of 'uname' in configure that won't work if you're cross-compiling. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1499955697-28045-1-git-send-email-peter.maydell@linaro.org
2017-06-29softfloat: define floatx80_round()Laurent Vivier1-0/+1
Add a function to round a floatx80 to the defined precision (floatx80_rounding_precision) Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170628204241.32106-5-laurent@vivier.eu>
2017-02-22softfloat: Add float128_to_uint32_round_to_zero()Bharata B Rao1-0/+1
float128_to_uint32_round_to_zero() is needed by xscvqpuwz instruction of PowerPC ISA 3.0. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22softfloat: Add float128_to_uint64_round_to_zero()Bharata B Rao1-0/+2
Implement float128_to_uint64() and use that to implement float128_to_uint64_round_to_zero() This is required by xscvqpudz instruction of PowerPC ISA 3.0. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22softfloat: Add round-to-odd rounding modeBharata B Rao1-0/+2
Power ISA 3.0 introduces a few quadruple precision floating point instructions that support round-to-odd rounding mode. The round-to-odd mode is explained as under: Let Z be the intermediate arithmetic result or the operand of a convert operation. If Z can be represented exactly in the target format, the result is Z. Otherwise the result is either Z1 or Z2 whichever is odd. Here Z1 and Z2 are the next larger and smaller numbers representable in the target format respectively. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xscvdphp, xscvhpdpBharata B Rao1-0/+20
xscvdphp: VSX Scalar round & Convert Double-Precision format to Half-Precision format xscvhpdp: VSX Scalar Convert Half-Precision format to Double-Precision format Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-15fpu: add mechanism to check for invalid long double formatsAndrew Dutcher1-0/+15
All operations that take a floatx80 as an operand need to have their inputs checked for malformed encodings. In all of these cases, use the function floatx80_invalid_encoding to perform the check. If an invalid operand is found, raise an invalid operation exception, and then return either NaN (for fp-typed results) or the integer indefinite value (the minimum representable signed integer value, for int-typed results). For the non-quiet comparison operations, this touches adjacent code in order to pass style checks. Signed-off-by: Andrew Dutcher <andrew@andrewdutcher.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1471392895-17324-1-git-send-email-andrew@andrewdutcher.com [PMM: changed "1 << 63" to "1ULL << 63" to fix compile errors] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-08-15softfloat: Fix warn about implicit conversion from int to int8_tPranith Kumar1-2/+2
Change the flag type to 'uint8_t' to fix the implicit conversion error. Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Message-id: 20160810185502.32015-1-bobby.prani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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