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2025-03-11system: Declare qemu_[min/max]rampagesize() in 'system/hostmem.h'Philippe Mathieu-Daudé1-3/+0
Both qemu_minrampagesize() and qemu_maxrampagesize() are related to host memory backends, having the following call stack: qemu_minrampagesize() -> find_min_backend_pagesize() -> object_dynamic_cast(obj, TYPE_MEMORY_BACKEND) qemu_maxrampagesize() -> find_max_backend_pagesize() -> object_dynamic_cast(obj, TYPE_MEMORY_BACKEND) Having TYPE_MEMORY_BACKEND defined in "system/hostmem.h": include/system/hostmem.h:23:#define TYPE_MEMORY_BACKEND "memory-backend" Move their prototype declaration to "system/hostmem.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-Id: <20250308230917.18907-7-philmd@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250311085743.21724-2-philmd@linaro.org Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-10migration: ram block cpr blockersSteve Sistare2-0/+4
Unlike cpr-reboot mode, cpr-transfer mode cannot save volatile ram blocks in the migration stream file and recreate them later, because the physical memory for the blocks is pinned and registered for vfio. Add a blocker for volatile ram blocks. Also add a blocker for RAM_GUEST_MEMFD. Preserving guest_memfd may be sufficient for CPR, but it has not been tested yet. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-ID: <1740667681-257312-1-git-send-email-steven.sistare@oracle.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-03-09Merge tag 'pull-tcg-20250308' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi8-409/+381
include/qemu: Tidy atomic128 headers. include/exec: Split out cpu-interrupt.h include/exec: Split many tlb_* declarations to cputlb.h include/accel/tcg: Split out getpc.h accel/tcg: system: Compile some files once linux-user/main: Allow setting tb-size # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmfMyz8dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9D/Af/Vh5PMtYjL+Mw2NQn # Vmqbv+joiqswAxI8PmZZzEBJ06j4pCLXn+r/2nr+sEwLmrI4BI40Vxx5c5puftoZ # GDGGclskF/pId5TE96TCEr8AoJgeNSSv4WxbINFTZRsRP4voZFHpU6mTz6B0Nnq5 # GS/k6c7+VcYbHIPD0RcIWwBlQv11uUAcnaygkNSsy+theUseOzTPTN/XGfTprf/6 # 1sxlmtt6QcQ88bBJJbiNwqbjWGxANcSUspRo0sstpVr8ApkXNl7WSkWYRBhBa5oc # iu0tixdCIoqqcCJy9/YVyIkmmwWeRUkbQqBeKf0o5xPnhmO3kfeezvERSDvDViAH # K9BVBw== # =7vra # -----END PGP SIGNATURE----- # gpg: Signature made Sun 09 Mar 2025 06:57:03 HKT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20250308' of https://gitlab.com/rth7680/qemu: (23 commits) accel/tcg: Build tcg-runtime-gvec.c once accel/tcg: Build tcg-runtime.c once qemu/atomic128: Include missing 'qemu/atomic.h' header qemu/atomic: Rename atomic128-ldst.h headers using .h.inc suffix qemu/atomic: Rename atomic128-cas.h headers using .h.inc suffix accel/tcg: Split out getpc.h accel/tcg: Restrict GETPC_ADJ to 'tb-internal.h' accel/tcg: Build tcg-accel-ops-mttcg.c once accel/tcg: Build tcg-accel-ops-rr.c once accel/tcg: Build tcg-accel-ops-icount.c once accel/tcg: Build tcg-accel-ops.c once system: Build watchpoint.c once exec: Declare tlb_flush*() in 'exec/cputlb.h' exec: Declare tlb_hit*() in 'exec/cputlb.h' exec: Declare tlb_set_page() in 'exec/cputlb.h' exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h' exec: Declare tlb_set_page_full() in 'exec/cputlb.h' exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h' accel/tcg: Compile watchpoint.c once include/exec: Split out exec/cpu-interrupt.h ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-08accel/tcg: Split out getpc.hRichard Henderson1-9/+1
Split out GETPC to a target-independent header. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250308072348.65723-3-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-03-08accel/tcg: Restrict GETPC_ADJ to 'tb-internal.h'Philippe Mathieu-Daudé1-9/+0
GETPC_ADJ is only used within accel/tcg/, no need to expose it to all the code base. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250308072348.65723-2-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-03-08exec: Declare tlb_flush*() in 'exec/cputlb.h'Philippe Mathieu-Daudé2-193/+191
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20241114011310.3615-19-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-03-08exec: Declare tlb_hit*() in 'exec/cputlb.h'Philippe Mathieu-Daudé1-23/+0
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-20-philmd@linaro.org>
2025-03-08exec: Declare tlb_set_page() in 'exec/cputlb.h'Philippe Mathieu-Daudé2-9/+11
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-18-philmd@linaro.org>
2025-03-08exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h'Philippe Mathieu-Daudé2-25/+28
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-17-philmd@linaro.org>
2025-03-08exec: Declare tlb_set_page_full() in 'exec/cputlb.h'Philippe Mathieu-Daudé2-22/+23
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-16-philmd@linaro.org>
2025-03-08exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h'Philippe Mathieu-Daudé3-3/+8
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20241114011310.3615-14-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-03-08include/exec: Split out exec/cpu-interrupt.hRichard Henderson3-65/+71
Some of these bits are actually common to all cpus; while the reset have common reservations for target-specific usage. While generic code cannot know what the target-specific usage is, common code can know what to do with the bits, e.g. single-step. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-03-07include/exec: Move TARGET_PAGE_{SIZE,MASK,BITS} to target_page.hRichard Henderson3-28/+51
Re-use the TARGET_PAGE_BITS_VARY mechanism to define TARGET_PAGE_SIZE and friends when not compiling per-target. Inline qemu_target_page_{size,mask,bits} as they are now trivial. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-03-07accel/tcg: Restrict CPU_TLB_DYN_*_BITS definitions to accel/tcg/Philippe Mathieu-Daudé1-26/+0
CPU_TLB_DYN_*_BITS definitions are only used by accel/tcg/cputlb.c and accel/tcg/translate-all.c. Move them to accel/tcg/tb-internal.h. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250305191859.71608-1-philmd@linaro.org>
2025-03-07include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGNPeter Maydell1-2/+6
Expand the example in the comment documenting MO_ATOM_SUBALIGN, to be clearer about the atomicity guarantees it represents. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250228103222.1838913-1-peter.maydell@linaro.org
2025-03-06include: Poison TARGET_PHYS_ADDR_SPACE_BITS definitionPhilippe Mathieu-Daudé1-0/+1
Ensure common code never use this target specific definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250305153929.43687-4-philmd@linaro.org>
2025-03-06accel/tcg: Restrict tlb_init() / destroy() to TCGPhilippe Mathieu-Daudé1-16/+0
Move CPU TLB related methods to accel/tcg/ scope, in "internal-common.h". Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-9-philmd@linaro.org>
2025-03-06qemu/compiler: Absorb 'clang-tsa.h'Philippe Mathieu-Daudé1-2/+0
We already have "qemu/compiler.h" for compiler-specific arrangements, automatically included by "qemu/osdep.h" for each source file. No need to explicitly include a header for a Clang particularity. Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250117170201.91182-1-philmd@linaro.org>
2025-02-19Merge tag 'pull-tcg-20250215-3' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2-12/+14
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS tcg: Cleanups after disallowing 64-on-32 tcg: Introduce constraint for zero register tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2 linux-user: Move TARGET_SA_RESTORER out of generic/signal.h linux-user: Fix alignment when unmapping excess reservation target/sparc: Fix register selection for all F*TOx and FxTO* instructions target/sparc: Fix gdbstub incorrectly handling registers f32-f62 target/sparc: fake UltraSPARC T1 PCR and PIC registers # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAme0tZ8dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+u+AgAi47VyMpkM8HvlvrV # 6NGYD5FANLAF+Axl42GCTZEsisLN8b+KNWnM3QIxtE/ryxVY+OBpn/JpMRN96MJH # jcbsbnadJxJEUktCi1Ny/9vZGKh/wfT45OdJ7Ej+J5J/5EIuDsJQEPlR5U4QVv7H # I574hNttTibj12lYs0lbo0hESIISL+ALNw+smBNYEQ5zZTAPl3utP96NiQ/w3lyK # qtybkljYXQRjOtUM7iNH2x6mwrBrPfbTDFubD0lLJGBTRQg2Q2Z5QVSsP4OY5gMp # L9NPEQPs35GXA8c0GcAWwhO6kAcEbvkcUEL+jhfalb5BWhVWBgmTqCqYXr5RvuG2 # flSRwg== # =BWCN # -----END PGP SIGNATURE----- # gpg: Signature made Wed 19 Feb 2025 00:30:23 HKT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20250215-3' of https://gitlab.com/rth7680/qemu: (28 commits) tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2 target/sparc: fake UltraSPARC T1 PCR and PIC registers target/sparc: Fix gdbstub incorrectly handling registers f32-f62 target/sparc: Fix register selection for all F*TOx and FxTO* instructions linux-user: Move TARGET_SA_RESTORER out of generic/signal.h elfload: Fix alignment when unmapping excess reservation tcg/sparc64: Use 'z' constraint tcg/riscv: Use 'z' constraint tcg/mips: Use 'z' constraint tcg/loongarch64: Use 'z' constraint tcg/aarch64: Use 'z' constraint tcg: Introduce the 'z' constraint for a hardware zero register include/exec: Use uintptr_t in CPUTLBEntry include/exec: Change vaddr to uintptr_t target/mips: Use VADDR_PRIx for logging pc_next target/loongarch: Use VADDR_PRIx for logging pc_next accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page plugins: Fix qemu_plugin_read_memory_vaddr parameters tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-02-18include/exec: Use uintptr_t in CPUTLBEntryRichard Henderson1-5/+5
Since we no longer support 64-bit guests on 32-bit hosts, we can use a 32-bit type on a 32-bit host. This shrinks the size of the structure to 16 bytes on a 32-bit host. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-18include/exec: Change vaddr to uintptr_tRichard Henderson1-7/+9
Since we no longer support 64-bit guests on 32-bit hosts, we can use a 32-bit type on a 32-bit host. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-12system/physmem: handle hugetlb correctly in qemu_ram_remap()William Roche1-1/+1
The list of hwpoison pages used to remap the memory on reset is based on the backend real page size. To correctly handle hugetlb, we must mmap(MAP_FIXED) a complete hugetlb page; hugetlb pages cannot be partially mapped. Signed-off-by: William Roche <william.roche@oracle.com> Co-developed-by: David Hildenbrand <david@redhat.com> Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20250211212707.302391-2-william.roche@oracle.com Signed-off-by: Peter Xu <peterx@redhat.com>
2025-02-12physmem: teach cpu_memory_rw_debug() to write to more memory regionsDavid Hildenbrand2-2/+6
Right now, we only allow for writing to memory regions that allow direct access using memcpy etc; all other writes are simply ignored. This implies that debugging guests will not work as expected when writing to MMIO device regions. Let's extend cpu_memory_rw_debug() to write to more memory regions, including MMIO device regions. Reshuffle the condition in memory_access_is_direct() to make it easier to read and add a comment. While this change implies that debug access can now also write to MMIO devices, we now are also permit ELF image loads and similar users of cpu_memory_rw_debug() to write to MMIO devices; currently we ignore these writes. Peter assumes [1] that there's probably a class of guest images, which will start writing junk (likely zeroes) into device model registers; we previously would silently ignore any such bogus ELF sections. Likely these images are of questionable correctness and this can be ignored. If ever a problem, we could make these cases use address_space_write_rom() instead, which is left unchanged for now. This patch is based on previous work by Stefan Zabka. [1] https://lore.kernel.org/all/CAFEAcA_2CEJKFyjvbwmpt=on=GgMVamQ5hiiVt+zUr6AY3X=Xg@mail.gmail.com/ Resolves: https://gitlab.com/qemu-project/qemu/-/issues/213 Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Link: https://lore.kernel.org/r/20250210084648.33798-8-david@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com>
2025-02-12memory: pass MemTxAttrs to memory_access_is_direct()David Hildenbrand1-2/+3
We want to pass another flag that will be stored in MemTxAttrs. So pass MemTxAttrs directly. Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Link: https://lore.kernel.org/r/20250210084648.33798-6-david@redhat.com [peterx: Fix MacOS builds] Signed-off-by: Peter Xu <peterx@redhat.com>
2025-02-12physmem: factor out direct access check into ↵David Hildenbrand1-3/+11
memory_region_supports_direct_access() Let's factor the complete "directly accessible" check independent of the "write" condition out so we can reuse it next. We can now split up the checks RAM and ROMD check, so we really only check for RAM DEVICE in case of RAM -- ROM DEVICE is neither RAM not RAM DEVICE. Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Link: https://lore.kernel.org/r/20250210084648.33798-4-david@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com>
2025-02-12physmem: factor out RAM/ROMD check in memory_access_is_direct()David Hildenbrand1-4/+6
Let's factor more of the generic "is this directly accessible" check, independent of the "write" condition out. Note that the "!mr->rom_device" check in the write case essentially disallows the memory_region_is_romd() condition again. Further note that RAM DEVICE regions are also RAM regions, so we can check for RAM+ROMD first. This is a preparation for further changes. Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Link: https://lore.kernel.org/r/20250210084648.33798-3-david@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com>
2025-02-12physmem: factor out memory_region_is_ram_device() check in ↵David Hildenbrand1-3/+10
memory_access_is_direct() As documented in commit 4a2e242bbb306 ("memory: Don't use memcpy for ram_device regions"), we disallow direct access to RAM DEVICE regions. Let's make this clearer to prepare for further changes. Note that romd regions will never be RAM DEVICE at the same time. Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Link: https://lore.kernel.org/r/20250210084648.33798-2-david@redhat.com Signed-off-by: Peter Xu <peterx@redhat.com>
2025-01-30Merge tag 'migration-20250129-pull-request' of ↵Stefan Hajnoczi2-4/+19
https://gitlab.com/farosas/qemu into staging Migration pull request - Purge of ram_save_target_page_legacy - Cleanups to postcopy, json writer, migration states - New migration mode cpr-transfer - Fix for a -Werror=maybe-uninitialized instance in savevm # -----BEGIN PGP SIGNATURE----- # # iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmeaT8EQHGZhcm9zYXNA # c3VzZS5kZQAKCRDHmNx0G+wxndXrEACTT+rdoEvOsNs4nM2a67GjxUoQZVTAWn+8 # lYhhNZLA4E+qHwpHTDCwyfyvCe615r72+bF7QO1KTrYeXGJg4SPk5kbEhCDqqjEu # SGqrlPwkC1x3WkTvb228iDddDQ8dccko3Sy6wAyz0o8dtp5p4iK+57qzB/84u94L # y3zQ+owOo9OLnXgdfMpN99HGQSvPR7CbP/2L293IrMCuPDUo9XhI7ARNS/phbT3Z # aDl10WGHKz1SJWOkPj137E6+xMKuCmOZDTufTcTaHfyliD04JRWgEZVnKJxKJDxd # 9e+lzHvXuYfO7YO11fr7DttPRnLEfjipELVTxrudM92eZ95XwdL4+ggfBTGHt76P # yFUrp7G8qsUjWd+DHPmoo6Gx71zPbE6v9J2NMn2/1k4WdPOYy7HTmDgCkRirRTvV # irYkHtdSFFsj3c0g4P4mhOzXnvUkGXzgrjteM5hlLy3bjSeZz9VMZADjiGqFGVPb # 6euPcLLa9oynkoP5UXmFd/9PjWcgnfIbQu2MVlIyWhjvTGZKSGecVZmH5pWTJuBV # xCbab1jYprRFpUIAMo94rgvRQRosomS1+GjGndFkX5++dTTlFSqpDLSGcEnPSGRx # o9n+IldNiqh2vjN1bj60pLfmrHN/F+hsGTsDJlW+kfeyBXBkGArg1rDjN5ae7GvD # UZK0N+OG0g== # =jwOI # -----END PGP SIGNATURE----- # gpg: Signature made Wed 29 Jan 2025 10:56:49 EST # gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D # gpg: issuer "farosas@suse.de" # gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown] # gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D * tag 'migration-20250129-pull-request' of https://gitlab.com/farosas/qemu: (42 commits) migration: refactor ram_save_target_page functions migration: Trivial cleanup on JSON writer of vmstate_save() migration: Merge precopy/postcopy on switchover start migration: Always set DEVICE state migration: Cleanup qemu_savevm_state_complete_precopy() migration: Unwrap qemu_savevm_state_complete_precopy() in postcopy migration: Notify COMPLETE once for postcopy migration: Take BQL slightly longer in postcopy_start() migration: Drop cached migration state in migration_maybe_pause() migration: Adjust locking in migration_maybe_pause() migration: Adjust postcopy bandwidth during switchover migration: Synchronize all CPU states only for non-iterable dump migration: Drop inactivate_disk param in qemu_savevm_state_complete* migration: Avoid two src-downtime-end tracepoints for postcopy migration: Optimize postcopy on downtime by avoiding JSON writer migration: Do not construct JSON description if suppressed migration: Remove postcopy implications in should_send_vmdesc() migration: cpr-transfer documentation migration-test: cpr-transfer tests/qtest: assert qmp connected ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-29memory: add RAM_PRIVATESteve Sistare1-0/+10
Define the RAM_PRIVATE flag. In RAMBlock creation functions, if MAP_SHARED is 0 in the flags parameter, in a subsequent patch the implementation may still create a shared mapping if other conditions require it. Callers who specifically want a private mapping, eg for objects specified by the user, must pass RAM_PRIVATE. After RAMBlock creation, MAP_SHARED in the block's flags indicates whether the block is shared or private, and MAP_PRIVATE is omitted. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/1736967650-129648-6-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-01-29physmem: qemu_ram_alloc_from_fd extensionsSteve Sistare1-4/+9
Extend qemu_ram_alloc_from_fd to support resizable ram, and define qemu_ram_resize_cb to clean up the API. Add a grow parameter to extend the file if necessary. However, if grow is false, a zero-sized file is always extended. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Link: https://lore.kernel.org/r/1736967650-129648-4-git-send-email-steven.sistare@oracle.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-01-23memattrs: Check the size of MemTxAttrsZhao Liu1-0/+2
Make sure MemTxAttrs is packed into 8 bytes and does not exceed 8 bytes. Suggested-by: Philippe Mathieu-Daudà <philmd@linaro.org> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250121151322.171832-3-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23memattrs: Convert unspecified member to boolZhao Liu1-7/+12
Convert `unspecified` member of MemTxAttrs from bit field to bool, so that bindgen could generate more ergonomic Rust binding with bool type. As a result, MemTxAttrs needs to be expanded from 4 bytes to 8 bytes. Therefore, move `unspecified` to after the bit fields and add reserved members to ensure that the whole structure is packed into 8 bytes. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250121151322.171832-2-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-17include/exec: remove warning_printed from MemoryRegionAlex Bennée1-1/+0
Since d197063fcf9 (memory: move unassigned_mem_ops to memory.c) this field is unused. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250116160306.1709518-31-alex.bennee@linaro.org>
2025-01-17include/exec: fix some copy and paste errors in kdocAlex Bennée1-2/+2
A number of copy and paste kdoc comments are referring to the wrong definition. Fix those cases. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250116160306.1709518-30-alex.bennee@linaro.org>
2025-01-17system: propagate Error to gdbserver_start (and other device setups)Alex Bennée1-1/+7
This started as a clean-up to properly pass a Error handler to the gdbserver_start so we could do the right thing for command line and HMP invocations. Now that we have cleaned up foreach_device_config_or_exit() in earlier patches we can further simplify by it by passing &error_fatal instead of checking the return value. Having a return value is still useful for HMP though so tweak the return to use a simple bool instead. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250116160306.1709518-11-alex.bennee@linaro.org>
2024-12-24accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_coreRichard Henderson1-14/+0
Convert all targets simultaneously, as the gen_intermediate_code function disappears from the target. While there are possible workarounds, they're larger than simply performing the conversion. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-20accel/tcg: Un-inline translator_is_same_page()Philippe Mathieu-Daudé1-8/+7
Remove the single target-specific definition used in "exec/translator.h" (TARGET_PAGE_MASK) by un-inlining is_same_page(). Rename the method as translator_is_same_page() and improve its documentation. Use it in translator_use_goto_tb(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241218154145.71353-1-philmd@linaro.org>
2024-12-20accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h'Philippe Mathieu-Daudé2-3/+3
The TranslationBlock flags are defined in 'exec/translation-block.h'. tcg_cflags_has/set() use them, it is more logical to declare them in the same place. Move them there too. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212144430.66224-2-philmd@linaro.org>
2024-12-20accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h'Philippe Mathieu-Daudé1-3/+0
curr_cflags() is only used within accel/tcg/, move its declaration to accel/tcg/internal-common.h. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241216214030.59393-1-philmd@linaro.org>
2024-12-20exec/translation-block: Include missing 'qemu/atomic.h' headerPhilippe Mathieu-Daudé1-0/+1
When moving tb_cflags() in commit 88d4b5138a8 ("tcg: Make tb_cflags() usable from target-agnostic code") we forgot to include "qemu/atomic.h", which declares qatomic_read(). Explicitly include it now to avoid issue when refactoring unrelated headers. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20241217141326.98947-2-philmd@linaro.org>
2024-12-20accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h'Philippe Mathieu-Daudé2-17/+18
Move cpu_loop_exit_requested() declaration to "exec/cpu-common.h", along with the related cpu_loop_exit_noexc(), cpu_loop_exit(), cpu_loop_exit_atomic() and cpu_loop_exit_restore() methods. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241217140648.98538-1-philmd@linaro.org>
2024-12-20exec/cpu-all: Include 'cpu.h' earlier so MMU_USER_IDX is always definedPhilippe Mathieu-Daudé1-1/+4
Include "cpu.h" earlier to get the MMU_USER_IDX definition soon enough and avoid when refactoring unrelated headers: In file included from include/exec/translator.h:271, from ../../accel/tcg/translator.c:13: include/exec/cpu-all.h: In function ‘cpu_mmu_index’: include/exec/cpu-all.h:274:12: error: ‘MMU_USER_IDX’ undeclared (first use in this function) 274 | return MMU_USER_IDX; | ^~~~~~~~~~~~ include/exec/cpu-all.h:274:12: note: each undeclared identifier is reported only once for each function it appears in ninja: build stopped: subcommand failed. We need to forward-declare cpu_mmu_index() to avoid on user emulation: In file included from include/exec/cpu-all.h:263, from include/exec/translator.h:271, from ../../accel/tcg/translator.c:13: ../../target/sparc/cpu.h: In function ‘cpu_get_tb_cpu_state’: ../../target/sparc/cpu.h:757:13: error: implicit declaration of function ‘cpu_mmu_index’ [-Werror=implicit-function-declaration] 757 | flags = cpu_mmu_index(env_cpu(env), false); | ^~~~~~~~~~~~~ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241218155202.71931-5-philmd@linaro.org>
2024-12-20user: Move various declarations out of 'exec/exec-all.h'Philippe Mathieu-Daudé1-54/+1
Move various declarations related to user emulation from "exec/exec-all.h" to "user/cpu_loop.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-19-philmd@linaro.org>
2024-12-20accel/tcg: Move user-related declarations out of 'exec/cpu-all.h' (4/4)Philippe Mathieu-Daudé1-6/+0
Move declarations related to page protection under user emulation from "exec/cpu-all.h" to "user/page-protection.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-15-philmd@linaro.org>
2024-12-20accel/tcg: Move user-related declarations out of 'exec/cpu-all.h' (3/4)Philippe Mathieu-Daudé1-12/+0
Move declarations related to page protection under user emulation from "exec/cpu-all.h" to "user/page-protection.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-14-philmd@linaro.org>
2024-12-20accel/tcg: Move user-related declarations out of 'exec/cpu-all.h' (2/4)Philippe Mathieu-Daudé1-55/+0
Move declarations related to page protection under user emulation from "exec/cpu-all.h" to "user/page-protection.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-13-philmd@linaro.org>
2024-12-20accel/tcg: Move user-related declarations out of 'exec/cpu-all.h' (1/4)Philippe Mathieu-Daudé1-5/+0
Move declarations related to page protection under user emulation from "exec/cpu-all.h" to "user/page-protection.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-12-philmd@linaro.org>
2024-12-20accel/tcg: Move 'exec/translate-all.h' -> 'tb-internal.h'Philippe Mathieu-Daudé1-28/+0
"exec/translate-all.h" is only useful to TCG accelerator, so move it to accel/tcg/, after renaming it 'tb-internal.h'. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-9-philmd@linaro.org>
2024-12-20accel/tcg: Move page_[un]protect() to 'user/page-protection.h'Philippe Mathieu-Daudé1-5/+0
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-7-philmd@linaro.org>
2024-12-20accel/tcg: Use tb_page_addr_t type in page_unprotect()Philippe Mathieu-Daudé1-1/+1
Match with the page_protect() prototype, use a tb_page_addr_t argument instead of target_ulong. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-6-philmd@linaro.org>
generated by cgit v1.1 at 2025-03-28 22:57:37 +0000